Dynamic DRAM Bad Cell Replacement via Address Match Table
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Solution Overview
Problem
As DRAM memory cells shrink due to advancements in process technology, they become more susceptible to errors from aging and repeated accesses, leading to reduced data retention time and increased variability in access transistor leakage, which conventional methods fail to adequately address.
Innovation Solution
Implementing a memory interface device with an address match table and control module that dynamically replaces faulty memory cells with spare cells, using a system of address match tables and multiplexers to reroute addresses and commands, allowing for transparent repair of bad memory cells and improving memory performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If DRAM memory cells are shrunk to increase memory capacity, then memory capacity increases, but data retention time decreases and leakage variability increases
Solution Approach 1:
The patent applies preliminary action by pre-identifying and mapping bad memory cell addresses during manufacturing or initialization. The address match table is pre-populated with bad addresses and their corresponding spare addresses, enabling proactive repair before actual memory operations encounter the defective cells. This preliminary mapping allows the system to dynamically redirect accesses away from problematic cells without impacting normal memory performance.
Solution Approach 2:
The patent introduces an intermediary component - the address match table - that sits between the memory controller and the physical memory array. This intermediary translates logical memory addresses to physical addresses, inserting a layer of indirection that enables bad addresses to be dynamically mapped to spare locations. The control module acts as another intermediary, monitoring memory operations and performing address substitution when bad cells are detected, thereby protecting the memory system from degradation without requiring physical cell replacement.
2Reliability
If conventional spare rows and columns are used for bad cell replacement, then bad cells can be repaired, but silicon area is wasted and memory capacity is reduced
Solution Approach 1:
The patent applies universality by making spare memory locations serve multiple purposes. Instead of dedicating entire spare rows and columns that can only be used for replacement, the system uses specific spare locations within the regular memory array that can serve both as functional memory cells and as replacement targets for bad cells. The address match table enables these spare locations to be dynamically assigned to different bad addresses as needed, maximizing the utility of limited spare resources while maintaining full memory array utilization.
Solution Approach 2:
The patent implements discarding and recovering by eliminating the need for permanent, dedicated spare rows and columns. Instead, the system recovers silicon area by using the address match table to dynamically allocate spare locations from the existing memory array. When bad cells are identified, their addresses are mapped to appropriate spare locations, and these spare locations are effectively recovered from the regular address space and repurposed for repair functions. This approach recovers the silicon area that would otherwise be wasted on unused spare structures.
3Reliability
If address match tables and control modules are added for dynamic replacement, then bad cell repair capability improves, but device complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the address translation function into discrete, manageable components. The address match table is organized as a structured data structure with separate entries for bad addresses and spare addresses, allowing systematic management of repair mappings. The control module processes address translation in discrete steps: receiving a logical address, checking the match table for bad addresses, and substituting with spare addresses when needed. This segmented approach makes the complexity modular and manageable rather than monolithic.
Solution Approach 2:
The patent uses copying by creating a virtual mapping layer through the address match table that copies the functionality of physical spare rows and columns into a software-based structure. Instead of duplicating physical memory structures, the system copies the address translation logic into a table data structure that can be manipulated in software. This virtual copying approach reduces hardware complexity while maintaining the essential repair functionality, as the match table can be updated and managed without physical hardware changes.
Data Source
AI summary
A memory device comprising an interface device and a plurality of memory arrays. The interface device includes an address match table comprising at least a revised address corresponding to a spare memory location and a control module configured to determine address information from the address stream from an address command bus coupled to the host controller during a run time operation. The control module is configured to compare each address from the address stream and determine whether each address matches with a stored address in the address match table to identify a bad address and configured to replace the bad address with the revised address of the spare memory location. The device also has a plurality of memory arrays. Each of the memory arrays comprises a plurality of memory cells. The memory device has a spare group of memory cells comprising a plurality of spare memory cells. Each of the plurality of spare memory cells being addressable using the address match table.