Dynamic ECC Allocation in NAND Flash Storage

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Solution Overview

Problem

NAND flash storage devices face challenges in in-place programming due to different unit sizes for read, write, and erase operations, leading to inefficiencies in write performance and error correction, which are exacerbated by the deterioration of cell quality over program-erase cycles, resulting in reduced endurance and reliability.

Innovation Solution

A method for determining an erase block score based on program-erase cycles and error correction parameters, allowing for dynamic allocation of overprovisioning and error correction spaces within each page, optimizing error correction overhead and overprovisioning to enhance programming speed and endurance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If error correction codes (ECC) are applied to correct bit errors in NAND flash, then data reliability is improved, but write performance deteriorates due to increased overhead and processing complexity

Engineering Contradiction:
Improvedata reliabilityVSAvoidwrite performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies different ECC strength levels to different page types within the same block. Specifically, it identifies that certain pages (e.g., pages with lower LSB significance or specific physical locations) have higher error susceptibility and applies stronger ECC to them, while using weaker ECC for more reliable pages. This local differentiation optimizes the balance between reliability and write performance by concentrating error correction resources where they are most needed.

Inventive Principle:
Principle #3Local quality

2Productivity

If over-provisioning is increased to reduce write amplification, then write performance is improved, but storage capacity is reduced

Engineering Contradiction:
Improvewrite performanceVSAvoidstorage capacity
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent dynamically adjusts the over-provisioning ratio based on the error characteristics of different page types. By changing the parameter of over-provisioning from a fixed value to a variable that depends on page reliability metrics, the system can optimize write performance for critical pages while maintaining adequate capacity for less critical pages, thereby improving overall write performance without excessive capacity loss.

Inventive Principle:
Principle #35Parameter changes

3Ease of manufacture

If uniform error correction is applied to all pages in a block, then implementation simplicity is maintained, but error correction efficiency deteriorates due to varying error susceptibility across different page types

Engineering Contradiction:
Improveimplementation simplicityVSAvoiderror correction efficiency
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent introduces page-type-specific error correction parameters that account for varying error susceptibility across different pages. It classifies pages into different types based on their error characteristics (e.g., based on LSB significance, physical location, or program-erase cycle history) and applies tailored ECC settings to each type. This approach maintains reasonable implementation complexity while significantly improving error correction efficiency compared to uniform treatment.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent implements dynamic error correction parameters that can be adjusted based on the program-erase cycle count and observed error patterns. The system monitors error rates and adjusts ECC strength accordingly, making the error correction strategy adaptive rather than static. This dynamic approach allows the system to optimize error correction efficiency as the NAND flash medium deteriorates over time.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11914470B2Efficient redundancy management in key-value NAND flash storage
Publication Date: 2024.02.27 PLIOPS LTD
  • US11914470B2 patent drawing
  • US11914470B2 patent drawing
  • US11914470B2 patent drawing

AI summary

A method for error correction of logical pages of an erase block of a solid state drive (SSD) memory, the method may include determining an erase block score of the erase block, wherein the calculating is based on a program erase (PE) cycle of the erase block and one or more erase block error correction parameter; determining, based on (a) the erase block score, and (b) a mapping between the erase block score and one or more page error correction parameters for each page type out of multiple pages types, the one or more page error correction parameter for each page type; and allocating, within each page of the erase block, an overprovisioning space and an error correction space, based on at least one page error correction parameter related to a page type of the page.