Dynamic ECC Check Field Expansion for Burst Memory Error Correction
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Solution Overview
Problem
Current data processing devices face high probabilities of error misdetection and miscorrection due to limitations in error correcting codes (ECC) when dealing with double-symbol errors, which is unacceptable in enterprise-class servers, and increasing checkbits to mitigate this issue increases memory size and latency.
Innovation Solution
The method dynamically increases ECC check field size in response to error situations, using error vectors to record and compare error locations during burst accesses, effectively enhancing error detection and correction capabilities while reducing the likelihood of miscorrection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of checkbits is increased to reduce error misdetection probability, then error detection reliability is improved, but memory size increases and cache line size compatibility is lost
Solution Approach 1:
The patent dynamically adjusts the check field size based on error detection needs. When a potential miscorrection is detected through syndrome analysis, the system expands the check field to include additional bits from subsequent memory beats, enabling more comprehensive error detection without permanently increasing memory allocation.
Solution Approach 2:
The patent nests additional check bits within existing memory beat structures. By organizing error detection across multiple nested memory beats (beat 0, beat 1, beat 2, etc.), the system effectively increases check field capacity while maintaining compatibility with standard cache line sizes and memory geometry.
2Reliability
If interleaving of data words is performed to reduce error misdetection, then error detection accuracy is improved, but memory access latency increases
Solution Approach 1:
The patent performs preliminary syndrome analysis on early memory beats to predict potential miscorrections before completing full data word retrieval. By detecting error patterns in intermediate beats, the system can identify cases requiring extended checking without waiting for complete interleaved data word assembly, thereby reducing latency.
Solution Approach 2:
The patent implements a fast path for error-free cases where syndrome analysis of initial beats confirms no errors exist, allowing the system to skip extended checking procedures and complete memory access quickly. Extended checking is only activated when necessary, reducing average access latency while maintaining high detection accuracy.
Data Source
AI summary
A method and device for error detection includes performing error detection for each data word received in a burst access to a memory. When no error is detected, the data words are written to a cache and indicated as valid data. In response to detecting an error in a data word, the error is corrected and the corrected data written to the cache without indicating the data as valid. In addition, the location of the detected error, indicating the data symbol associated with the error, is recorded in an error vector. The error vectors associated with each data word in the burst access are compared to determine whether a detected error was properly corrected.