Dynamic On-Die ECC Control for Memory Self-Test
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Solution Overview
Problem
Memory devices face challenges in detecting and repairing single-bit errors (SBEs) and multiple-bit errors (MBEs) during in-field testing, as existing error-correcting codes (ECC) may mask SBEs when enabled, and disabling ECC is necessary for comprehensive testing, but this requires manual intervention and can be resource-intensive.
Innovation Solution
The memory device is enabled to automatically or selectively disable on-die ECC during built-in self-test (MBIST) operations, allowing for testing of both SBEs and MBEs based on mode register settings, enabling the detection and repair of errors without manual intervention and optimizing resource usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If on-die ECC is enabled during MBIST, then error correction capability is improved, but single-bit error detection is worsened due to masking
Solution Approach 1:
The patent implements dynamic switching of ECC functionality based on test requirements. The mode register allows the system to enable or disable on-die ECC during MBIST operations, transitioning between different operational states to optimize for either error correction or single-bit error detection depending on the specific test phase and requirements
2Measurement precision
If on-die ECC is disabled for comprehensive testing, then error detection capability is improved, but device complexity and manual intervention requirements increase
Solution Approach 1:
The patent enables the memory device to automatically manage ECC disabling and re-enabling during MBIST operations through mode register configuration. This self-service mechanism eliminates the need for manual intervention to disable ECC for testing, as the system autonomously transitions between ECC-enabled and ECC-disabled states based on the test phase, thereby reducing testing complexity while maintaining comprehensive error detection capability
3Measurement precision
If manual intervention is used to disable ECC for testing, then error detection is improved, but productivity and time efficiency are worsened
Solution Approach 1:
The patent implements preliminary configuration through mode register settings that automatically trigger ECC disabling before MBIST operations begin. This preliminary action ensures that the system is pre-configured for comprehensive error detection without requiring manual intervention during the actual testing process, thereby improving productivity and time efficiency while maintaining accurate error detection capability
Data Source
AI summary
Implementations described herein relate to enabling or disabling on-die error-correcting code for a memory built-in self-test. A memory device may read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device. The memory device may identify, based on the one or more bits, whether the memory built-in self-test is to be performed with on-die error-correcting code (ECC) disabled or with on-die ECC enabled. The memory device may perform the memory built-in self-test, and selectively test for one or more single-bit errors, based on identifying whether the memory built-in self-test is to be performed with the on-die ECC disabled or with the on-die ECC enabled.