Dynamic ECC Evaluation for Single-Cycle Memory Validation
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Solution Overview
Problem
In high-frequency memory devices, the logic delay associated with calculating and comparing error correcting codes (ECCs) exceeds one clock cycle, leading to inefficiencies and reduced bandwidth, as existing solutions either prolong clock cycles or reduce memory device frequency.
Innovation Solution
Implementing a logic path that uses dynamic logic gates to complete ECC calculations and comparisons, allowing the process to be clock-cycle-independent, thereby reducing the overall delay to less than one clock cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If static logic gates are used to calculate and compare ECC values, then the calculation can be completed, but the logic delay exceeds one clock cycle, reducing bandwidth
Solution Approach 1:
The patent applies dynamic logic gates instead of static logic gates to perform ECC calculation and comparison. The dynamic logic circuit can complete the ECC validation within one clock cycle by utilizing the dynamic nature of the logic gates, which allows faster switching and reduced propagation delay compared to static gates. This resolves the contradiction by maintaining reliable ECC validation while improving productivity through faster processing that keeps pace with high-frequency memory operations.
2Reliability
If clock cycle duration is extended to accommodate ECC calculation delay, then ECC validation can be completed, but memory device frequency is reduced
Solution Approach 1:
The dynamic logic gates enable the ECC calculation and comparison to complete within a single clock cycle without requiring extension of the clock cycle duration. The dynamic nature of the logic circuit allows it to operate at the same high frequency as the memory device, maintaining both reliability of ECC validation and high operating speed.
3Reliability
If two clock periods are used for ECC validation, then the calculation can be completed, but the processing time increases
Solution Approach 1:
The dynamic logic circuit performs both ECC calculation and comparison in parallel within a single clock cycle, eliminating the need for two sequential clock periods. This reduces the validation time while maintaining accurate error detection and correction validation.
Solution Approach 2:
The patent merges the ECC calculation and comparison operations into a single integrated dynamic logic circuit that performs both functions simultaneously within one clock cycle, rather than separating them into distinct sequential steps that would require multiple clock periods.
Data Source
AI summary
Error correcting codes (ECCs) have been proposed to be used in high frequency memory devices to detect errors in signals transmitted between a memory controller and a memory device. For high frequency memory devices, ECCs have delay characteristics of greater than one clock cycle. When the delay exceeds one clock cycle but is much less than two clock cycles, an entire second clock cycle must be added. By calculating and comparing the ECC value in a static logic circuit and a dynamic logic circuit, the logic delay is substantially reduced. In addition, the ECC value may be calculated and compared using two sets of static logic gates, where the second static logic gate is clocked by a clock signal that is delayed relative to the clock signal of the first set of logic gates.