Dynamic ECC Code Rate Adjustment for MLC Memory Bit Errors
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Solution Overview
Problem
As memory devices scale down, bit errors become increasingly problematic due to decreased charge retention in Multi Level Cell (MLC) memories, leading to a non-static bit error rate that affects data integrity.
Innovation Solution
A system comprising a memory array, an error control coding engine, and a bit error rate monitor dynamically adjusts the code rate by changing the length of codewords and the number of maximum corrections based on monitored bit error rates, ensuring the bit error rate remains within a desired threshold.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory devices are scaled down to increase storage density, then storage capacity is improved, but bit error rate increases due to decreased charge retention
Solution Approach 1:
The patent implements dynamic adjustment of ECC code rate based on real-time monitoring of bit error rates. The system transitions from static error correction to a dynamic system that adapts code rate parameters according to actual memory conditions, allowing optimal balance between storage capacity and data reliability under varying operational states
Solution Approach 2:
The system changes key parameters including code rate, codeword length, and error correction capability based on monitored bit error rates. By adjusting these parameters dynamically, the system maintains data integrity while maximizing storage utilization as memory characteristics degrade over time or with scaling
2Reliability
If a fixed high code rate is used to maintain low bit error rate, then data integrity is improved, but storage capacity is reduced
Solution Approach 1:
The system dynamically adjusts code rate based on actual bit error rate conditions rather than using a fixed high code rate. This allows the system to maintain data integrity when errors occur while maximizing storage capacity during normal operation, eliminating the need to permanently operate at conservative error correction levels
Solution Approach 2:
The patent implements variable code rate and codeword length parameters that adapt to memory conditions. When bit error rates are low, the system uses higher code rates for maximum capacity; when error rates increase, the system adjusts parameters to enhance error correction capability, thus optimizing the trade-off between integrity and capacity
3Quantity of substance
If a fixed low code rate is used to maximize storage capacity, then storage capacity is improved, but bit error rate increases
Solution Approach 1:
The system transitions from static low code rate operation to dynamic adjustment where code rate increases automatically when bit error rates exceed thresholds. This ensures the system maintains high storage capacity during normal operation while providing enhanced error protection when memory degradation or errors are detected
Solution Approach 2:
The patent implements a feedback mechanism where bit error rates are continuously monitored and used to adjust code rate parameters. This closed-loop control allows the system to respond to actual error conditions, increasing protection only when and where needed, thus maintaining high capacity while preventing error accumulation
4Reliability
If error correction capability is increased to reduce outgoing bit error rate, then data reliability is improved, but device complexity increases
Solution Approach 1:
The system implements dynamic error correction capability that adjusts based on actual bit error rate conditions rather than maintaining fixed high-level protection. This allows the system to achieve low outgoing error rates when needed while reducing complexity during normal operation, optimizing the balance between reliability and device complexity
Data Source
AI summary
A method, apparatus, and system for dynamic adjustment of an error control coding (ECC) code rate are disclosed. In one embodiment, a code rate may be changed from a first code rate to a second code rate in response to a change in a bit error rate.