Dynamic ECC Region Sizing in Nonvolatile Cache Memory

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Nonvolatile memory systems, such as MRAM, face high error rates due to access frequency, aged deterioration, and environmental changes, which affect data reliability and require efficient error correction mechanisms.

Innovation Solution

A cache memory system with a nonvolatile memory comprising a first region for storing data and a second region for storing ECCs, where an error corrector generates and applies ECCs for data correction, an error rate detector adjusts the size of the second region based on error rates, and a reliability control unit manages refresh operations to maintain data integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by stationary object

If nonvolatile memory is used for cache memory to reduce standby energy and increase integration, then energy efficiency and integration density are improved, but error rate increases due to access frequency, aged deterioration, and environmental changes

Engineering Contradiction:
Improvestandby energyVSAvoiderror rate
Core Design Contradiction:
Use of energy by stationary objectVSReliability

Solution Approach 1:

The nonvolatile memory is divided into multiple banks, and the ECC mechanism is applied selectively to specific banks based on their error rates. This segmentation allows the system to focus error correction resources on problematic areas while maintaining energy efficiency in other regions.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system dynamically changes the ECC configuration parameters based on measured error rates. When error rates exceed thresholds, the system activates or strengthens ECC mechanisms for specific memory banks, thereby adapting the reliability level to actual operational conditions.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If ECC mechanism is added to correct errors in nonvolatile memory, then data reliability is improved, but device complexity and overhead increase

Engineering Contradiction:
Improvedata reliabilityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Instead of applying uniform ECC across the entire nonvolatile memory, the system applies ECC selectively to specific memory banks that exhibit high error rates. This local quality approach ensures that complexity is introduced only where necessary, rather than across the whole system.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The ECC configuration is made dynamic rather than static. The system monitors error rates and adjusts ECC activation and strength dynamically based on actual memory bank performance, allowing the complexity level to adapt to changing conditions.

Inventive Principle:
Principle #15Dynamics

3Device complexity

If fixed ECC size is used in nonvolatile memory, then device complexity is reduced, but adaptability to varying error rates decreases

Engineering Contradiction:
Improvedevice complexityVSAvoidadaptability to error rates
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The system implements dynamic adjustment of ECC size based on measured error rates. When error rates increase, the ECC size is increased to provide stronger correction capability, and when error rates decrease, the ECC size is reduced. This dynamic behavior provides adaptability without requiring a fully complex static configuration.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The ECC configuration parameters, particularly the size of the ECC code, are changed based on operational conditions and error rate measurements. This allows the system to adapt its error correction capability to match actual environmental and operational factors.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10360100B2Cache memory system and processor system
Publication Date: 2019.07.23 KIOXIA CORP
  • US10360100B2 patent drawing
  • US10360100B2 patent drawing
  • US10360100B2 patent drawing

AI summary

A cache memory system has a nonvolatile memory which includes a first region and a second region, the first region storing readable and writable data, the second region storing an ECC for correcting an error of the data in the first region, an error corrector which generates the ECC and carries out an error correction of the data in the first region with the ECC, error rate determination circuitry which determines an error rate of the data in the first region, and region size adjustment circuitry which adjusts a size of the second region inside the nonvolatile memory based on the error rate.