Dynamic Error Correction Table for Read-Disturb Memory
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Solution Overview
Problem
As memory technologies scale in size and density, the tighter margins for data sensing and increased disturbance from high-speed memory cell accesses lead to limitations in error correction capabilities, necessitating improved error correction code (ECC) performance while minimizing hardware overhead.
Innovation Solution
An error correcting table is embedded on integrated circuit memory devices, dynamically tracking and correcting errors between write or refresh operations using content addressable memory (CAM) to prevent ECC limit exceedance during sequential reads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multibit ECC technologies such as BCH codes are applied to correct multiple bit errors, then error correction capability is improved, but hardware overhead increases significantly
Solution Approach 1:
The error correction function is segmented into two parts: a lightweight dynamic error correction table that tracks and corrects accumulated errors, and the traditional ECC logic that handles residual errors. This segmentation allows the system to achieve multibit error correction capability without implementing complex multibit ECC codes, thereby reducing hardware overhead while maintaining reliability
Solution Approach 2:
The system performs preliminary error correction by proactively tracking and correcting errors as they accumulate during read operations, before the total error count exceeds the ECC correction capability. This preliminary action prevents error accumulation from reaching levels that would require complex multibit ECC, thus reducing the needed hardware overhead
2Productivity
If memory cells are accessed at high speed and high volume, then productivity is improved, but memory cell disturbance increases causing more errors
Solution Approach 1:
The system implements feedback by continuously monitoring errors during read operations and dynamically updating the error correction table. This feedback mechanism allows the system to adapt to accumulating errors caused by high-speed access and read disturb effects, maintaining reliability while preserving high productivity
Solution Approach 2:
The error correction table automatically tracks and corrects errors without requiring external intervention or complex control logic. The system self-adjusts by populating and updating the correction table based on observed errors, enabling it to handle high-volume accesses while compensating for the increased disturbance and read disturb effects
3Reliability
If error correction capability is extended to handle accumulated errors, then reliability is improved, but ECC limits may be exceeded
Solution Approach 1:
The system performs preliminary correction of accumulated errors using the dynamic error correction table before the total error count reaches the ECC correction limit. By proactively correcting errors as they accumulate, the system prevents the situation where corrected errors plus new errors would exceed the ECC capability, thus avoiding information loss
Solution Approach 2:
The error correction table acts as an intermediary between the memory array and the ECC logic. It captures and corrects a portion of the errors, reducing the error burden on the ECC logic and preventing the combined error load from exceeding ECC limits, thereby maintaining reliability without losing information
Data Source
AI summary
A dynamic error correcting table can be embedded on an integrated circuit memory device. The error correcting table includes entries which are created for data when an error is detected and corrected during a read of the data. During subsequent reads, without intervening write or refresh operations, the entry in the table can be used to correct the error by merging the corrected bit with the data output from the array before it is applied to the ECC logic.