Dynamic Equalizer Gain Control for High-Speed Data Reception
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Solution Overview
Problem
High-speed data transmission in liquid crystal panel modules is hindered by parasitic resistance and fluctuations in power supply and temperature, leading to signal degradation and limitations in increasing bit rate due to the difficulty in dynamically controlling the equalizer gain in conventional analog front-end circuits.
Innovation Solution
A data reception device with an equalizer circuit, clock data recovery (CDR) circuit, oversampler, and calibration control unit that dynamically adjusts the gain value and phase alignment of the clock signal, using a feedback loop to optimize signal recovery and transmission quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the bit rate is increased to support higher resolution panels, then the data transmission capability is improved, but the signal degradation due to parasitic resistance becomes more severe
Solution Approach 1:
The equalizer gain is made dynamically adjustable through multiple gain stages (first gain stage and second gain stage) that can be selectively activated. This allows the system to adapt the equalization strength based on the operating bit rate and channel conditions, providing strong equalization at high bit rates while maintaining signal integrity.
Solution Approach 2:
The patent changes the equalizer gain parameter dynamically by switching between different gain stages. The first gain stage provides a first gain value and the second gain stage provides a second gain value, allowing the system to optimize the equalization parameter according to the transmission conditions and bit rate requirements.
2Reliability
If the equalizer gain is increased to compensate for signal degradation, then the signal quality is improved, but the power consumption increases
Solution Approach 1:
The equalizer gain is dynamically controlled based on the operating bit rate. At lower bit rates, the first gain stage is sufficient and consumes less power. When the bit rate increases and signal degradation becomes severe, the second gain stage is activated to provide additional equalization. This dynamic adaptation ensures optimal signal quality while minimizing power consumption.
Solution Approach 2:
The patent implements partial equalization at lower bit rates using the first gain stage, and only activates the second gain stage when necessary at higher bit rates. This avoids applying excessive equalization (and associated power consumption) when it is not needed, achieving energy-efficient operation across different transmission conditions.
3Reliability
If the clock and data lines are separated to reduce interference, then the signal integrity is improved, but the timing skew between clock and data increases
Solution Approach 1:
The patent introduces a delay element as an intermediary component in the data path to compensate for the timing skew caused by separating clock and data lines. This delay element adjusts the data signal timing to align with the clock signal, eliminating timing skew while maintaining the benefits of separated lines for reduced interference.
4Measurement precision
If multiple source drivers are used to support high resolution panels, then the display resolution is improved, but the number of interfaces and parts increases
Solution Approach 1:
The timing controller is designed with multi-functionality to control multiple source drivers through a single interface. The equalizer and CDR circuits can serve multiple data lanes, and the controller can dynamically allocate resources to different source drivers based on resolution requirements, reducing the total number of interfaces and parts needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables high-speed operation and stabilization of transmission quality even in environments with high parasitic resistance, reducing power consumption and cost by dynamically controlling the equalizer gain and timing skew, thus supporting higher resolution and faster data transfer.
Implementation Method 1
an equalizer circuit 11 that shapes a waveform of an input signal according to a set gain value
Implementation Method 2
a PLL type CDR circuit 12 that recovers one clock signal from the input signal after being subjected to the waveform shaping performed by the equalizer circuit 11
Data Source
AI summary
A data reception device includes: an equalizer circuit that shapes a waveform of an input signal according to a set gain value; a CDR circuit which recovers a plurality of clock signals having different phases in one cycle from the input signal after being subjected to the waveform shaping performed by the equalizer circuit; an oversampler which performs sampling of the waveform-shaped input signal in synchronization with the plurality of clock signals and recovers a plurality of input data from the waveform-shaped input signal; and a calibration control unit which determines whether the oversampler correctly recovers the input data based on a result of the sampling performed by the oversampler, and generates a control signal to set the gain value of the equalizer circuit based on a determination result when it is determined that the input data is not correctly recovered.