Dynamic Logic Equivalence Check Mode Switching

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Solution Overview

Problem

Modern circuit design synthesis optimizations, such as timing optimizations and state minimization, often invalidate the matched register hypothesis used in equivalence checking, leading to reconstruction flaws and inefficient sequential equivalence checking that consumes excessive computational resources.

Innovation Solution

A system implementing a logic equivalence check tool that dynamically switches between combinational and sequential equivalence check modes, using matched register pairs to sub-divide and analyze combinational logic, and iteratively expand non-equivalent logic portions to determine equivalence.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If synthesis optimizations (timing optimizations, state minimization) are applied to convert design representations, then productivity and manufacturing precision are improved, but the matched register hypothesis becomes invalid leading to equivalence checking failures

Engineering Contradiction:

Improvedesign synthesis efficiencyVSAvoidequivalence checking accuracy

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The equivalence checking tool dynamically changes its analysis mode between combinational and sequential based on the presence of optimization indicators. When optimization indicators are detected in the guidance file, the tool switches from combinational mode to sequential mode, adapting its behavior to the actual design characteristics rather than relying on static assumptions about register matching.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The tool changes its operational parameters (analysis mode) based on detected optimization conditions. The mode change is triggered by specific parameters in the guidance file that indicate the presence of timing optimizations or state minimization, allowing the tool to adjust its equivalence checking strategy to match the optimized design structure.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If sequential equivalence checking is used to verify optimized designs, then equivalence checking accuracy is improved, but computational resource consumption increases exponentially

Engineering Contradiction:

Improveequivalence checking accuracyVSAvoidcomputational resource consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The tool dynamically selects between combinational and sequential equivalence checking modes based on optimization detection. When optimizations are present, it uses sequential mode for accuracy; when optimizations are absent or after handling optimized portions, it returns to combinational mode to reduce computational overhead. This dynamic adaptation prevents the exponential resource consumption of pure sequential checking while maintaining accuracy where needed.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The equivalence checking process is segmented into different modes (combinational and sequential) that are applied selectively based on the design characteristics. The tool divides the checking process into portions that require sequential analysis (where optimizations are present) and portions that can use faster combinational analysis, reducing overall computational resource consumption while maintaining accuracy where required.

Inventive Principle:

Principle #1Segmentation

3Productivity

If combinational equivalence checking is used for unoptimized designs, then computational efficiency is improved, but the tool fails to accurately check optimized designs

Engineering Contradiction:

Improveequivalence checking speedVSAvoidequivalence checking accuracy

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The tool dynamically adjusts its analysis mode based on the detection of optimization indicators in the guidance file. For unoptimized designs or unoptimized portions, it operates in fast combinational mode. When optimization indicators are detected, it switches to sequential mode to ensure accurate equivalence checking, thus adapting its behavior to match the actual design characteristics rather than using a fixed approach.

Inventive Principle:

Principle #15Dynamics

4Reliability

If reconstruction techniques are used to recreate 1-to-1 register matching, then matched register hypothesis is restored, but reconstruction flaws increase and independent analysis is eliminated

Engineering Contradiction:

Improvematched register hypothesis validityVSAvoidreconstruction complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

Instead of trying to reconstruct the original design to match the synthesized design (the conventional approach), the tool inverts the approach by analyzing the synthesized design as-is and adapting the equivalence checking method to accommodate the optimizations. It uses the guidance file to detect optimizations and adjusts its analysis mode accordingly, eliminating the need for error-prone reconstruction while maintaining the ability to verify equivalence.

Inventive Principle:

Principle #13The other way round (Inversion)

Data Source

PatentUS9477805B2Logical equivalency check with dynamic mode change

Publication Date: 2016.10.25 SIEMENS INDUSTRY SOFTWARE INC

AI summary

This application discloses a system implementing tools and mechanisms to determine whether a portion of combinational logic in a first circuit design is equivalent to a portion of combinational logic in a second circuit design. When the portions of the combinational logic in the first circuit design and the second circuit design are not equivalent, the tools and mechanisms can sequentially expand the portions of the combinational logic in the first circuit design and the second circuit design, and determine whether the expanded portion of the combinational logic in the first circuit design is equivalent the expanded portion of the combinational logic in the second circuit design.