Dynamic Erase Step Voltage Control for 3D NAND Memory
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Solution Overview
Problem
Traditional incremental step pulse erase (ISPE) schemes for NAND flash memory can result in either deep or shallow erase, leading to degraded endurance and reduced read margin due to the predetermined erase voltage and step voltage, which do not account for varying endurance of memory cells across different memory blocks.
Innovation Solution
A method that incrementally increases the first erase voltage until initial erase verification is passed, followed by sub-erase verifications to determine the second erase voltage, which is adjusted based on the results of these verifications to ensure precise reset of memory cells to the erase state, avoiding deep or shallow erase.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a predetermined erase voltage and incrementing step voltage are applied to all memory cells, then the erase operation can be performed uniformly across memory blocks, but the erase depth becomes uncontrolled resulting in either deep erase or shallow erase
Solution Approach 1:
The patent implements dynamic adjustment of the erase step voltage based on verification results. The erase step voltage is not fixed but is modified according to the pass/fail status of verification operations, allowing the system to adapt the erase depth control to the actual state of memory cells, thereby resolving the contradiction between uniform operation and precise control.
Solution Approach 2:
The patent introduces a feedback mechanism where verification operations are performed after erase operations, and the results of these verifications are used to adjust subsequent erase parameters. This closed-loop control ensures that the erase depth is precisely controlled by continuously monitoring and adjusting the erase step voltage based on actual memory cell states.
2Manufacturing precision
If verification operations are performed after each erase step to determine pass or fail, then the erase depth can be controlled more precisely, but the overall erase time increases
Solution Approach 1:
The patent performs verification operations selectively rather than after every single erase step. By determining when verification is necessary based on the erase process state and adjusting the erase step voltage accordingly, the system achieves precise erase depth control without requiring verification after each minor erase step, thus reducing overall time consumption.
Solution Approach 2:
The patent performs preliminary verification operations at strategic points during the erase process to determine the appropriate erase step voltage for subsequent steps. By anticipating the needed adjustments based on early verification results, the system avoids unnecessary verification operations later, optimizing the balance between precision and time efficiency.
3Device complexity
If a fixed erase step voltage is used for all memory blocks, then the erase process is simpler to implement, but memory cells with different endurance experience cannot be properly erased
Solution Approach 1:
The patent makes the erase step voltage dynamic rather than fixed. The voltage is adjusted based on verification results, allowing the system to adapt to different memory block endurance characteristics. This dynamic approach maintains relatively simple implementation while achieving adaptability to varying endurance levels across different memory blocks.
Solution Approach 2:
The patent changes the erase step voltage parameter based on observed memory cell behavior during verification. By modifying this critical parameter according to actual performance data, the system achieves adaptability to different endurance levels without requiring complex pre-characterization or classification of memory blocks.
Data Source
AI summary
The present disclosure provides a method of erase and erase verification for a memory device. The method includes applying a first erase voltage to erase memory cells of the memory device. The first erase voltage is incrementally increased by a first erase step voltage until the memory cells pass an initial erase verification. The method also includes determining whether the memory cells pass or fail sub-erase verifications by applying sub-erase verification voltages. The method further includes applying a second erase voltage to erase the memory cells after the sub-erase verifications. The second erase voltage is increased from the first erase voltage by a second erase step voltage, which is smaller than the first erase step voltage and is determined according to whether the memory cells pass or fail the sub-erase verifications.