Dynamic Erase Voltage Adjustment in Non-Volatile Memory
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Solution Overview
Problem
Non-volatile memory devices experience performance degradation due to structural degradation from repeated programming and erase cycles, leading to increased erase loops and elevated threshold voltage, which results in inefficiencies in programming speed and power consumption.
Innovation Solution
A method and system for dynamically adjusting the erase voltage level by monitoring the number of erase/verify loops and adjusting the initial erase voltage to ensure it meets a pre-defined threshold count, thereby optimizing the number of erase loops required to achieve the 'erased' state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of programming and erase cycles increases to maintain storage capacity, then storage density is improved, but structural degradation occurs leading to performance decline
Solution Approach 1:
The system performs preliminary characterization of the non-volatile memory structure by conducting initial programming and erase operations to establish baseline performance parameters. This preliminary action enables the system to detect degradation trends before they significantly impact storage capacity, allowing for proactive adjustment of operational parameters to maintain performance stability over extended cycles.
Solution Approach 2:
The system continuously monitors performance parameters during programming and erase operations and uses this feedback to dynamically adjust operational parameters. By comparing current performance against baseline characteristics and detecting degradation trends, the system modifies subsequent operations to compensate for structural changes, thereby maintaining stable performance despite increasing cycle counts.
2Reliability
If erase loops are increased to ensure complete erase, then erase completeness is improved, but time consumption increases
Solution Approach 1:
The system dynamically adjusts the number of erase loops based on real-time monitoring of erase effectiveness. Instead of using a fixed number of loops, the system adapts the erase operation parameters according to the specific characteristics and degradation state of the memory structure, optimizing the balance between ensuring complete erase and minimizing time consumption.
Solution Approach 2:
The system replaces fixed mechanical erase loop counting with an intelligent control mechanism that monitors electrical characteristics during erase operations. By substituting rigid procedural repetition with adaptive parameter adjustment based on measured electrical properties, the system achieves more efficient erase operations that maintain completeness while reducing time requirements.
3Speed
If higher voltage is applied during erase operations to speed up the process, then erase speed is improved, but power consumption increases
Solution Approach 1:
The system dynamically changes operational parameters including voltage levels during programming and erase operations based on the current state of the non-volatile memory structure. By adjusting voltage parameters in response to monitored performance characteristics and degradation trends, the system optimizes the balance between erase speed and power consumption, applying higher voltages only when and where necessary to achieve effective erasure.
4Duration of action of stationary object
If the memory structure is used for extended periods, then storage capacity utilization is improved, but structural degradation increases
Solution Approach 1:
The system performs preliminary characterization and continuous monitoring of the non-volatile memory structure's performance parameters throughout its operational life. By establishing baseline characteristics and detecting degradation trends early, the system can take preliminary corrective actions such as adjusting operational parameters or initiating maintenance procedures to preserve structural integrity over extended periods.
Solution Approach 2:
The system implements self-diagnosis and self-adjustment capabilities by continuously monitoring its own performance parameters and automatically modifying operational parameters to compensate for degradation. This self-service approach enables the memory structure to maintain stable performance and structural integrity throughout its operational lifespan without requiring external intervention or maintenance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach helps maintain optimal erase loop counts, preventing over-programming and reducing power consumption, thus enhancing the efficiency and speed of erase operations in non-volatile memory devices.
Implementation Method 1
each memory cell is comprised of a floating gate that is positioned above and isolated from a channel region of a semiconductor substrate, wherein the floating gate is positioned between the source and drain regions
Implementation Method 2
the threshold voltage (Vth) of the resulting transistor is controlled by and dependent upon an amount of charge that is retained on the floating gate
Implementation Method 3
a minimum amount of voltage that must be applied to the control gate before the transistor is activated to permit conduction between its source and drain regions
Implementation Method 4
bit-value data can be programmed onto and erased from the memory cell by precisely changing the level of charge on a floating gate
Data Source
AI summary
A method for dynamically adjusting an erase voltage level to be applied in a subsequent erase cycle, comprising: in a current erase cycle, initiating a current erase/verify loop by applying an initial stored erase voltage level according to an erase sequence in which each successive erase/verify loop is incremented by a pre-determined voltage amount, storing an erase/verify loop count, and determining whether the current erase cycle is complete according to a pass criterion. If the erase cycle is complete, a determination is made as to whether the stored erase/verify loop count equals a pre-defined threshold count. Further, if the stored count does not equal the pre-defined threshold count, the initial stored erase voltage level is adjusted such that, upon applying the adjusted erase voltage level in a subsequent erase cycle, an erase/verify loop count will now equal the pre-defined threshold count.