Dynamic Erase Voltage Pulse Adjustment for NAND Flash Memory
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Solution Overview
Problem
Existing erase operations in NAND flash memory systems face challenges in efficiently adjusting erase voltage pulses, leading to over erasure for lower program/erase cycles and inadequate erasure for higher cycles, due to fixed voltage and duration settings.
Innovation Solution
Implementing a self-adaptive, dynamic adjustment of erase voltage pulses based on the number of program/erase cycles, using two different erase verify voltages and pulses to ensure accurate erasure across varying cycle counts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If fixed voltage and duration settings are used for erase operations, then the erase operation is simple to implement, but it causes over erasure for lower program/erase cycles and inadequate erasure for higher cycles
Solution Approach 1:
The patent implements dynamic adjustment of erase voltage pulses based on the number of program/erase cycles. The erase voltage magnitude and/or duration are modified according to the cycle count, transitioning from fixed settings to adaptive settings that respond to the actual state of the memory cells, thereby resolving the contradiction between implementation simplicity and erase accuracy.
Solution Approach 2:
The patent changes the parameters of the erase voltage pulse (magnitude and/or duration) based on the number of program/erase cycles. By adjusting these parameters dynamically, the system achieves accurate erasure across different cycle conditions while maintaining a relatively simple implementation through automated parameter selection.
2Reliability
If erase voltage pulse magnitude and duration are increased to ensure deep erasure for high cycle counts, then adequate erasure is achieved for worn cells, but over erasure occurs for new memory cells
Solution Approach 1:
The patent applies different erase voltage characteristics (magnitude and/or duration) tailored to the specific condition of the memory cells based on their program/erase cycle history. New cells receive lower voltage or shorter duration pulses, while worn cells receive higher voltage or longer duration pulses, ensuring each cell group receives the appropriate erasure treatment without unnecessary damage.
Solution Approach 2:
The erase voltage parameters are dynamically adjusted based on the number of program/erase cycles, allowing the system to adapt the erasure strength to the actual needs of the memory cells, preventing both over erasure and inadequate erasure.
3Manufacturing precision
If multiple erase voltage pulses with varying magnitudes are applied, then accurate erasure is achieved across different cycle counts, but the erase operation complexity increases
Solution Approach 1:
The patent manages the complexity of multiple erase voltage pulses by systematically varying parameters (magnitude and/or duration) based on the number of program/erase cycles. This structured approach to parameter changes achieves accurate erasure while keeping the control logic relatively simple through automated parameter selection based on cycle count.
Data Source
AI summary
An example method includes, performing a first erase verify on a first set of memory cells of a portion of an array of memory cells, performing a second erase verify on a second set of memory cells of the portion of the array, applying a first erase voltage pulse concurrently to each memory cell in the portion of the array if the first set fails the first erase verify and if the second set fails the second erase verify, and applying a second erase voltage pulse concurrently to each memory cell in the portion of the array if the first set passes the first erase verify and if the second set fails the second erase verify. The second erase voltage pulse is different than the first erase voltage pulse.