Dynamic Erase Voltage Step for 3D NAND Flash Memory
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Solution Overview
Problem
Precise erase voltage control is critical for 3D-Nand flash products to prevent intrinsic NAND cell reliability risks such as lateral charge loss and over-erase, which existing methods fail to address effectively, leading to compromised performance and reliability.
Innovation Solution
A dynamic erase voltage step is determined to accommodate block-to-block variation, reducing the risk of intrinsic cell reliability degradation by dynamically adjusting the erase voltage, thereby achieving high erase performance without compromising NAND cell reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a fixed erase voltage is applied to all blocks, then the erase operation is simple to implement, but block-to-block variation in erase depth occurs leading to reliability issues
Solution Approach 1:
The patent applies dynamics by transitioning from a fixed erase voltage to a dynamic erase voltage that changes based on block-specific characteristics. The controller determines a unique erase voltage for each block based on its threshold voltage distribution and block type, allowing the system to adapt to block-to-block variations while maintaining reliability.
Solution Approach 2:
The patent implements local quality by applying different erase voltages to different blocks based on their specific characteristics. Each block receives a customized erase voltage tailored to its threshold voltage distribution and block type (e.g., SLC vs MLC), ensuring optimal erase depth for each local region rather than using a uniform approach.
2Productivity
If a high erase voltage is applied to ensure complete erasure, then erase performance improves, but over-erase occurs causing lateral charge loss and reliability degradation
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the erase voltage parameter based on block characteristics such as threshold voltage distribution and block type. The controller calculates an optimal erase voltage for each block that achieves complete erasure without excessive voltage that would cause over-erase and lateral charge loss, thus maintaining both performance and reliability.
Solution Approach 2:
The patent implements feedback by using threshold voltage distribution information and block type data to determine the appropriate erase voltage for each block. This feedback mechanism allows the controller to select erase voltages that achieve the desired erase depth while preventing over-erase conditions that would harm cell reliability.
3Reliability
If a dynamic erase voltage is applied to each block based on block characteristics, then block-to-block variation in erase depth is reduced improving reliability, but the complexity of the erase operation increases
Solution Approach 1:
The patent manages the complexity of dynamic voltage adjustment by implementing a systematic approach where the controller determines erase voltages based on pre-characterized block types and threshold voltage distributions. This dynamic approach improves reliability by reducing block-to-block variation while keeping the complexity manageable through automated determination processes.
Data Source
AI summary
Apparatuses, systems, and methods for determining a dynamic erase voltage step. One example apparatus can include an array of memory cells and a controller coupled to the array of memory cells, wherein the controller is configured to apply a first erase voltage to a first wordline and a second wordline in the array of memory cells to perform an erase operation, apply a first verify voltage to the first wordline to verify the erase operation, apply a second verify voltage greater than the first verify voltage to the second wordline in response to failing to verify the erase operation by applying the first verify voltage to the first wordline, and apply a second erase voltage to the first wordline and the second wordline in response to verifying the erase operation by applying the second verify voltage to the second wordline.