Dynamic Erase Voltage Step Size for 3D Non-Volatile Memory
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Solution Overview
Problem
3D stacked non-volatile memory devices face challenges in efficiently erasing memory cells due to degradation from over-erase and decreased erase speed as program-erase cycles accumulate, leading to prolonged erase times.
Innovation Solution
The solution involves dynamically adjusting the erase voltage step size based on the number of program-erase cycles, using data such as a count of cycles or loop count from programming operations to optimize the erase process, ensuring accurate and efficient erasure without over-erase or prolonged times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed erase voltage step size is used, then the erase process is simple, but memory cell degradation occurs due to over-erase and erase speed decreases as program-erase cycles accumulate
Solution Approach 1:
The patent applies dynamics by transitioning from a fixed erase voltage step size to a dynamic step size that adapts based on the number of program-erase cycles. The erase voltage step size is increased as the cycle count increases, allowing the system to maintain optimal erase performance throughout the memory device's lifecycle and prevent over-erase degradation.
Solution Approach 2:
The patent changes the parameter of erase voltage step size dynamically based on the program-erase cycle count. By modifying this critical parameter according to the device's operational history, the system optimizes erase effectiveness while preventing over-erase, thereby improving reliability without requiring complex additional hardware.
2Productivity
If a fixed erase voltage step size is used, then the control mechanism is simple, but total erase time increases due to decreased erase speed over time
Solution Approach 1:
The system dynamically adjusts the erase voltage step size based on the number of program-erase cycles. As cycles accumulate and erase speed naturally decreases, the adaptive mechanism increases the step size to compensate, maintaining consistent erase performance and reducing total erase time throughout the device's operational life.
Solution Approach 2:
The patent implements feedback by monitoring the number of program-erase cycles and using this information to adjust the erase voltage step size. This closed-loop approach ensures that the erase process adapts to changing conditions, maintaining optimal speed and preventing time loss due to degradation.
3Loss of time
If a larger erase voltage step size is used, then erase time is reduced, but over-erase degradation increases
Solution Approach 1:
The patent resolves this contradiction by making the step size dynamic rather than fixed. The system starts with a smaller step size to prevent over-erase in early cycles, then progressively increases it as the device ages. This adaptive approach allows the system to minimize erase time in later stages while preventing over-erase degradation through controlled progression.
Solution Approach 2:
The patent applies preliminary action by establishing a conservative initial erase voltage step size that prevents over-erase in the early stages of the device lifecycle. Only after accumulating sufficient program-erase cycles does the system safely increase the step size, ensuring that over-erase is prevented throughout the entire operational period while still achieving acceptable erase times.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents memory cell degradation, maintains erase speed, and reduces total erase time by adapting the erase voltage step size according to the device's cycle count, ensuring optimal performance over time.
Implementation Method 1
The techniques are directed toward using tunneling current to erase memory cells
Data Source
AI summary
Techniques are provided for erasing memory cells in a 3D stacked non-volatile memory device in a way which avoids prolonging erase time as the erase speed deceases due to the accumulation of program-erase cycles. In particular, a step size for erase pulses can be set which is a function of the number of program-erase cycles, e.g., as indicated by a count of program-erase cycles, a loop count during programming which is a function of programming speed, or an initial program voltage which is a function of programming speed. Further, the erase operation can account for different erase speeds of memory cells in different word line layers.