Dynamic Pull-Down ESD Clamp Circuit for Noise-Tolerant Protection
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Solution Overview
Problem
Existing ESD protection circuits face challenges in achieving both noise tolerance during operation and sufficient breakdown voltage performance due to the fixed resistance value of the pull-down resistor, which affects the protection of semiconductor devices from static electricity and high ESD voltages.
Innovation Solution
The ESD protection circuit incorporates a power MOS transistor, a clamp circuit, and a MOS transistor with adjustable pull-down resistance, switching between 2 kΩ and 100 kΩ based on the operation status of the protection target circuit, utilizing a series connection of resistors and capacitors to manage voltage and current effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the resistance value of the pull-down resistor is increased, then the clamp voltage decreases, but the power transistor becomes apt to turn ON in an unintended manner due to external noise during operation
Solution Approach 1:
The patent applies the dynamics principle by making the resistance value of the pull-down resistor changeable based on the operation status of the protection target circuit. A control circuit dynamically adjusts the resistance between a first value (during operation) and a second value (higher than the first, during non-operation). This allows the circuit to have low resistance during operation to prevent noise-induced turn-ON, and high resistance during non-operation to achieve low clamp voltage for ESD protection.
2Object-affected harmful factors
If the resistance value of the pull-down resistor is decreased, then the noise tolerance during operation improves, but the clamp voltage increases making it unachievable to protect the protection target circuit from static electricity when high ESD voltage is applied
Solution Approach 1:
The patent implements dynamic resistance adjustment where the pull-down resistor switches between a first resistance value (lower, for noise tolerance during operation) and a second resistance value (higher, for ESD protection during non-operation). This dynamic behavior resolves the contradiction by providing the appropriate resistance value for each operational state.
Solution Approach 2:
The patent changes the resistance parameter of the pull-down resistor based on the operation status of the protection target circuit. By adjusting this key parameter between two distinct values, the circuit achieves both noise tolerance during operation and ESD breakdown voltage performance during non-operation.
3Device complexity
If a fixed resistance value is used for the pull-down resistor, then the circuit structure is simple, but it is difficult to achieve both noise tolerance during operation and breakdown voltage performance with respect to ESD voltage
Solution Approach 1:
The patent transitions from a fixed resistance structure to a dynamic resistance structure controlled by a control circuit that monitors the operation status of the protection target circuit. This added complexity enables the circuit to achieve both noise tolerance and ESD breakdown voltage performance by adjusting the resistance value appropriately for each operational state.
Solution Approach 2:
The patent introduces a control mechanism that changes the resistance parameter based on operational conditions. This parameter change capability allows the circuit to optimize performance for both noise tolerance during operation and ESD protection during non-operation, resolving the limitation of fixed resistance designs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for optimal noise tolerance during operation and enhanced ESD breakdown voltage performance by dynamically adjusting the pull-down resistance, effectively protecting semiconductor devices from both noise and high ESD voltages.
Implementation Method 1
a first capacitor coupled in series between a second node coupled to the third line and the second line
Data Source
AI summary
An ESD protection circuit includes a power MOS transistor disposed between a first line and a second line, a clamp circuit disposed between the first line and a first node to which a gate of the power MOS transistor is coupled, a first resistor disposed between the first node and the second line, a MOS transistor disposed between the first node and the second line, a third line supplied with a third potential generated by a constant-voltage circuit of the protection target circuit, and a second resistor and a first capacitor coupled in series between a second node coupled to the third line and the second line, wherein when defining a junction between the second resistor and the first capacitor as a third node, a gate of the MOS transistor is coupled to the third node.