Dynamic ESD Protection Circuit for CMOS IC Power-On Events
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Solution Overview
Problem
Existing ESD protection circuits are ineffective in protecting integrated circuit chips from power-on and power-off ESD events, as they fail to provide a low impedance current path during chip operation and power-up conditions, leading to potential chip damage.
Innovation Solution
The implementation of an ESD protection circuit with power-on zap circuits, ESD voltage comparators, and a discharge mechanism that activates during ESD events, ensuring a low resistance path for ESD current flow even when the chip is powered up, by using a combination of upper and lower ESD diodes, esdPlus and esdMinus rails, and an ESD switch circuit with an RC time constant.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ESD switch remains closed during normal operation, then ESD protection is always active, but chip malfunction occurs due to DC paths
Solution Approach 1:
The ESD switch circuit's impedance is made dynamic rather than static. During normal operation, the switch remains in high impedance state (effectively open), preventing DC paths and chip malfunction. During ESD events, it transitions to low impedance state (closed) to provide protection. This dynamic behavior resolves the contradiction by ensuring protection availability only when needed, not during normal operation.
Solution Approach 2:
The power-on detection circuit provides feedback about the power supply state to the ESD switch circuit. This feedback mechanism allows the switch circuit to sense whether it should be active (during power-on ESD events) or inactive (during normal operation), preventing chip malfunction while maintaining protection capability. The feedback control resolves the contradiction between always-active protection and normal operation compatibility.
2Reliability
If ESD switch closes during power-up, then ESD protection is provided, but VDD power supply is shorted to VSS
Solution Approach 1:
The power-on detection circuit performs preliminary detection of the power supply state before the ESD switch circuit activates. By detecting whether VDD is in a stable or transitioning state beforehand, the circuit prevents premature activation during normal power-up, avoiding the harmful shorting effect while still providing protection when actually needed during power-on ESD events.
Solution Approach 2:
The power-on detection circuit acts as an intermediary between the power supply and the ESD switch circuit. It monitors the power supply state and conditionally enables the switch circuit only when appropriate, preventing direct harmful interaction between VDD and VSS during normal power-up while allowing protection during ESD events. This intermediary control resolves the contradiction between protection and power supply stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively protects the chip from both power-on and power-off ESD events by ensuring a low impedance current path during ESD occurrences, preventing damage and maintaining normal chip operation.
Implementation Method 1
an ESD switch circuit with an RC time constant
Implementation Method 2
a combination of upper and lower ESD diodes
Data Source
AI summary
An electrostatic discharge protection circuit (ESD protection circuit) provides ESD protection to all NMOS/PMOS transistors that are connected to the pins of a CMOS integrated circuit (IC). The ESD protection circuit will protect the CMOS IC against an ESD event, regardless of whether the CMOS IC is powered up, or powered down.