Dynamic Fault Handling Mode Switching in Processing Circuitry

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Solution Overview

Problem

Existing CPU fault handling mechanisms face challenges in identifying the 'owner' of memory access faults, especially in systems with multiple applications and exception handling routines, where asynchronous fault reporting can lead to ambiguity and performance issues.

Innovation Solution

The processing circuitry is designed to switch between synchronous and asynchronous fault handling modes based on the current context, applying constraints to ensure faults are reported before proceeding beyond a recovery point in synchronous mode, and removing constraints in asynchronous mode, allowing for dynamic switching between modes during execution.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If synchronous fault handling mode is used, then fault identification capability is improved, but instruction execution throughput deteriorates

Engineering Contradiction:

Improvefault identification capabilityVSAvoidinstruction execution throughput

Core Design Contradiction:

Measurement precisionVSProductivity

Solution Approach 1:

The processor dynamically switches between synchronous and asynchronous fault handling modes based on the current execution context. When executing critical code portions where accurate fault identification is essential, the processor operates in synchronous mode to maintain state information. When executing non-critical code, it switches to asynchronous mode to maximize throughput, thus adaptively resolving the contradiction between fault identification capability and instruction execution throughput.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

Different fault handling strategies are applied to different code regions. Critical code portions that require accurate fault identification are handled synchronously, while non-critical code portions are handled asynchronously. This local differentiation allows the system to optimize fault handling for specific contexts without sacrificing overall performance.

Inventive Principle:

Principle #3Local quality

2Productivity

If asynchronous fault handling mode is used, then instruction execution throughput is improved, but fault recovery complexity increases

Engineering Contradiction:

Improveinstruction execution throughputVSAvoidfault recovery complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The processor dynamically adjusts fault handling mode based on execution context, switching to synchronous mode when fault recovery simplicity is critical and to asynchronous mode when throughput is prioritized. This dynamic adaptation allows the system to manage fault recovery complexity only when necessary, rather than incurring it continuously.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

Asynchronous fault handling is applied selectively to non-critical code portions where throughput optimization is more important than simple fault recovery. Critical code portions continue to use synchronous handling, ensuring that complexity is incurred only where it provides the most value.

Inventive Principle:

Principle #3Local quality

3Loss of information

If synchronous fault handling mode is used, then state information availability is improved, but execution speed deteriorates

Engineering Contradiction:

Improvestate information availabilityVSAvoidexecution speed

Core Design Contradiction:

Loss of informationVSSpeed

Solution Approach 1:

Inventive Principle:

Principle #15Dynamics

4Ease of manufacture

If asynchronous fault handling mode is used, then implementation simplicity is improved, but fault identification accuracy deteriorates

Engineering Contradiction:

Improveimplementation simplicityVSAvoidfault identification accuracy

Core Design Contradiction:

Ease of manufactureVSMeasurement precision

Solution Approach 1:

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS10394641B2Apparatus and method for handling memory access operations

Publication Date: 2019.08.27 ARM LTD

AI summary

An apparatus and method are described for handling memory access operations, and in particular for handling faults occurring during the processing of such memory access operations. The apparatus has processing circuitry for executing program instructions that include memory access instructions, and a memory interface for coupling the processing circuitry to a memory system. The processing circuitry is switchable between a synchronous fault handling mode and an asynchronous fault handling mode. When in the synchronous fault handling mode the processing circuitry applies a constraint on execution of the program instructions such that a fault resulting from a memory access operation processed by the memory system will be received by the memory interface before the processing circuitry has allowed program execution to proceed beyond a recovery point for the memory access instruction associated with the memory access operation. In contrast, when in the asynchronous fault handling mode, the processing circuitry removes that constraint. The processing circuitry is then arranged to switch between the synchronous fault handling mode and the asynchronous fault handling mode during execution of the program instructions, in dependence on a current context of the processing circuitry. This enables the apparatus to selectively take advantage of the higher performance associated with asynchronous reporting of faults, and the improved fault handling associated with the synchronous reporting of faults.