Dynamic Current-Mode FIR Filter for Fine-Pitch Pixel Circuits
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Solution Overview
Problem
Conventional current-mode FIR filters require large transistors to mitigate mismatch, making them unsuitable for compact applications like in-pixel filtering in image sensors with fine pixel pitches.
Innovation Solution
A dynamic current-mode FIR filter utilizing dynamic current mirrors and multipliers, which employ dynamically configured transistors to perform filtering operations, allowing for compact and efficient circuit design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional current-mode circuits are used in FIR filters, then filtering accuracy is maintained, but circuit area becomes too large for fine pixel pitches
Solution Approach 1:
The patent employs dynamic current mirrors and dynamically configured transistors that switch between different circuit configurations during operation. This dynamic reconfiguration allows the same hardware to perform multiple filtering operations sequentially, reducing the overall circuit area while maintaining filtering accuracy through precise current control during each phase
Solution Approach 2:
The FIR filter operates through periodic phases including a first phase for computing partial sums and a second phase for computing final output values. This periodic operation allows time-multiplexed use of circuit elements, enabling accurate filtering computations to be completed within constrained area by reusing the same transistors and current mirrors across different time periods
2Measurement precision
If large transistors are used to mitigate mismatch, then filtering precision is improved, but device area increases beyond acceptable limits
Solution Approach 1:
The patent uses dynamically configured transistors that change their role and configuration between operational phases. During the first phase, transistors are configured for computing partial sums; during the second phase, the same transistors are reconfigured for computing final output values. This dynamic reconfiguration reduces the need for oversized transistors while maintaining precision through controlled current operations at each phase
Solution Approach 2:
The patent changes the operational parameters of transistors between phases by altering their connection topology and control signals. This parameter change allows the same physical transistor to achieve different functional states with appropriate current control, eliminating the need to increase transistor area to improve precision
3Area of stationary object
If compact circuits are designed for fine pixel pitches, then area constraints are satisfied, but circuit complexity increases
Solution Approach 1:
The patent segments the filtering operation into distinct phases: a first phase for computing partial sums and a second phase for computing final output values. This temporal segmentation allows complex filtering computations to be broken into simpler sequential steps, reducing the instantaneous circuit complexity while maintaining compact area through phased operation
Solution Approach 2:
The patent designs universal current mirrors and dynamically configured transistors that perform multiple functions across different phases. The same circuit elements compute both partial sums and final outputs, eliminating the need for separate dedicated circuits for each function. This multi-functionality reduces overall circuit complexity while satisfying area constraints through efficient resource reuse
Data Source
AI summary
The proposed dynamic current-mode finite impulse response (FIR) filter includes a coefficient signal generator to generate a coefficient signal, an input signal generator to generate an input signal, a dynamic current multiplier configured to receive the input signal and the coefficient signal and to generate intermediate product terms that are multiplications of the coefficient values and reflected and shifted input values, and an accumulator configured to receive the intermediate product terms and to sequentially integrate the intermediate product terms over the coefficient values to produce output responses for the input values. The dynamic current multiplier includes a first dynamically configured transistor (DCT) having a first input node to receive the first input signal during a first phase of operation and a second input node to receive the second input signal during a second phase of operation, and a second DCT having an input node to receive a third input signal during a first phase of operation, and output the intermediate product terms during a second phase of operation.