Dynamic Flash Memory Cell Segmentation for Stable Data Retention
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Solution Overview
Problem
Dynamic flash memory cells experience a decrease in operation margin and data retention performance due to changes in floating body channel voltage and discharge of signal charges, which are not adequately addressed in existing memory technologies.
Innovation Solution
A semiconductor-element-including memory device with a structure featuring a semiconductor body, impurity regions, gate insulator layers, and gate conductor layers, where voltage control is used to manage positive holes during page erase and write operations, ensuring minimal current flow between impurity regions and optimizing capacitance configurations for stable data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single MOS transistor is used to form a memory cell without a capacitor, then device complexity is reduced and integration density is improved, but operation margin decreases and data retention performance deteriorates due to floating body channel voltage changes and signal charge discharge
Solution Approach 1:
The memory cell is divided into multiple functional regions: a first region with a first gate electrode for programming, and a second region with a second gate electrode for reading. This segmentation allows independent control of charge storage and charge detection, resolving the contradiction between simple structure and reliable operation.
Solution Approach 2:
A floating body channel is introduced as an intermediary charge storage medium between the gate electrodes and the substrate. This floating body acts as a mediator that retains charge without requiring an external capacitor, enabling both low complexity and adequate retention through its isolated charge storage capability.
2Ease of operation
If voltage is applied to the selected word line to read data, then data reading operation is enabled, but capacitive coupling causes large floating body channel voltage changes that reduce operation margin
Solution Approach 1:
The memory cell is divided into a first region with a first gate electrode for programming and a second region with a second gate electrode for reading. By separating the programming and reading functions into different regions with independent gate electrodes, the patent enables data reading without causing large voltage changes in the floating body channel, thus maintaining operation margin.
Solution Approach 2:
The floating body channel serves as an intermediary that decouples the reading operation from the charge storage region. When voltage is applied to the second gate electrode for reading, the floating body channel acts as an intermediary that allows voltage application without causing large capacitive coupling effects in the charge storage region, thereby maintaining stable operation margin.
3Ease of manufacture
If impact ionization is used to generate and store positive holes in the channel, then data writing is achieved, but signal charge discharge occurs that reduces data retention performance
Solution Approach 1:
The memory cell is segmented into a first region for programming with a first gate electrode and a second region for reading with a second gate electrode. This segmentation allows the programming operation to be confined to the first region while the second region maintains stable charge storage, reducing signal charge discharge and improving data retention performance.
Solution Approach 2:
The floating body channel acts as an intermediary charge storage medium that is electrically isolated from the substrate. This intermediary structure prevents signal charge discharge to the substrate while still allowing impact ionization to generate and store positive holes during the programming operation, thereby maintaining both writing capability and retention performance.
4Productivity
If multiple pages are erased simultaneously to improve productivity, then processing time is reduced, but current consumption increases and control complexity increases
Solution Approach 1:
The first gate electrode and second gate electrode are designed to serve multiple functions: the first gate electrode controls both programming of the first region and can be used for erasing, while the second gate electrode controls reading and can also be used for erasing. This multi-functionality enables simultaneous erasure of multiple pages through unified voltage control, improving productivity without proportionally increasing control complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables stable rewriting operations with low power consumption, reduces data retention issues, and enhances system speed by allowing simultaneous erasure of multiple pages with minimal current usage, thereby improving the reliability and performance of dynamic flash memory cells.
Implementation Method 1
the floating body channel voltage of a selected memory cell connected to the selected word line changes to a large degree due to capacitive coupling between the gate electrode and the channel
Implementation Method 2
a group of positive holes and electrons generated inside the channel by an impact ionization phenomenon caused by a current between the source and the drain of the N-channel MOS transistor
Data Source
AI summary
A memory device includes pages arranged in a column direction and each constituted by memory cells arranged in a row direction on a substrate, each memory cell includes a semiconductor body, first and second impurity regions, and first and second gate conductor layers, the first and second impurity regions and first and second gate conductor layers are connected to source, bit, word, and plate lines respectively, and voltages applied to these lines are controlled to perform an erase operation of collecting a group of positive holes in the semiconductor body of a selected memory cell in a part adjacent to the first gate conductor layer and making some of the group of positive holes disappear and a page write operation of increasing by an impact ionization phenomenon, the number of positive holes in the semiconductor body of a selected memory cell in a page.