Dynamic Flip-Flop Latch Using Weak Keeper to Cut Leakage

The flip-flop is divided into master and slave sections with separate clock phases. The master latch captures data on one clock phase while the slave latch holds data on the other phase, segmenting the data path to prevent leakage-induced errors while maintaining compact area.

The patent employs dynamic clocked latches where transistors are periodically activated and deactivated based on clock signals. This dynamic operation allows the circuit to maintain data while controlling leakage currents through timed transistor switching, resolving the contradiction between area efficiency and reliability.

The patent uses periodic clock signals to control the master and slave latches alternately. During the first clock phase, the master latch is active and slave is held; during the second phase, roles reverse. This periodic action enables high-speed operation while preventing glitches and leakage from corrupting data by ensuring proper timing isolation.

The slave latch acts as an intermediary between the master latch and the output. It receives data from the master latch during one clock phase and transfers it to the output during the next phase, mediating the data flow to prevent direct exposure to leakage currents and glitches while maintaining high-speed operation.

The patent pre-charges and pre-discharges specific nodes during defined clock phases to prepare the latches for data capture. This preliminary action ensures that when data is latched, the circuit is in the correct state, preventing leakage currents from causing storage loss while maintaining the simplified dynamic architecture.

The patent changes the operational parameters of transistors dynamically through clock-controlled gating. By periodically activating and deactivating transistor channels based on clock phases, the circuit achieves low leakage during hold phases while maintaining functionality during active phases, resolving the contradiction between simplicity and energy loss.