Dynamic D Flip-Flop Data Retention Circuit for Leakage Control

The flip-flop is divided into multiple latch units (first latch unit, second latch unit, third latch unit) that operate in a pipeline manner. Each latch unit captures and holds data at different clock phases, allowing the overall system to maintain data retention while operating at higher frequencies. The segmentation of the single latch into multiple sequential latches distributes the data holding function across time phases.

The first latch unit performs preliminary data capture and holding before the second latch unit processes the data. By pre-capturing data in the first latch unit during the first clock phase, the system ensures data is already stored and stable before subsequent processing occurs, preventing data loss even at high operation frequencies.

Multiple latch units are merged into a single integrated flip-flop structure with shared clock signal terminals and coordinated operation. The first, second, and third latch units work together as a unified data retention system, combining their individual data holding capabilities to achieve extended overall data retention time while maintaining a relatively compact structure.

The latch units operate in periodic cycles synchronized by clock signals. The first latch unit captures data during the first clock phase, the second latch unit processes it during the second clock phase, and the third latch unit outputs during the third clock phase. This periodic operation allows each latch to be refreshed regularly, preventing data loss from leakage while maintaining structural simplicity.