Dynamic D Flip-Flop Circuit With Three-State Latch for Lower Chip Area
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Solution Overview
Problem
Existing D flip-flops in computing devices for mining virtual digital currency occupy large chip area, result in slow operation speed, and difficulty in controlling electric leakage, due to high transistor count and complex analog switch control.
Innovation Solution
A dynamic D flip-flop design with a first latch unit, a second latch unit, and an output driving unit, where the second latch unit is a three-state inverter using low leakage PMOS and NMOS transistors, and the output driving unit uses high threshold voltage devices, reducing chip area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional D flip-flop circuits using multiple analog switches and inverters are used, then data storage and transmission functions are achieved, but chip area occupation increases significantly
Solution Approach 1:
The patent combines multiple separate components (analog switches and inverters) into an integrated circuit structure with shared transistors. The first and second analog switches share PMOS and NMOS transistors, and the first and second inverters share transistors, reducing the total component count and chip area while maintaining the data storage and transmission functions.
Solution Approach 2:
The circuit design makes transistors serve multiple functions. For example, the PMOS and NMOS transistors in the analog switches serve both as switching elements and as part of the inverter structures. This multi-functionality reduces the overall transistor count from sixteen to fewer transistors, directly reducing chip area.
2Area of stationary object
If dynamic D flip-flop with separate analog switches and inverters is used, then chip area is reduced, but access speed becomes slow
Solution Approach 1:
The patent merges the analog switch and inverter functions into a unified circuit structure where transistors serve dual purposes. This integration reduces the number of discrete components and interconnections, thereby reducing signal propagation delay and improving access speed while maintaining reduced chip area.
Solution Approach 2:
The circuit is segmented into functional units (first latch unit with analog switch and inverter, second latch unit with analog switch and inverter, output driving unit) that can operate semi-independently. This segmentation allows for optimized signal paths within each unit, improving access speed while keeping the overall area reduced.
3Reliability
If conventional D flip-flop with multiple transistors is used, then data latching function is reliable, but control of electric leakage becomes difficult
Solution Approach 1:
The patent combines control functions into fewer transistors that serve multiple purposes. The shared transistors between analog switches and inverters reduce the total number of elements that need to be controlled, simplifying the control logic while maintaining reliable data latching through the coordinated operation of the merged components.
Data Source
AI summary
The invention provides a dynamic D flip-flop, and a data operation unit, a chip, a hash board and a computing device using the same. The dynamic D flip-flop comprises: an input terminal, an output terminal and at least one clock signal terminal; a first latch unit for transmitting data of the input terminal and latching the data under control of a clock signal; a second latch unit for latching data of the output terminal and inversely transmitting the data latched by the first latch unit under control of a clock signal; and an output driving unit for inverting and outputting the data received from the second latch unit; wherein the second latch unit outputs in high level, low level and high impedance states by means of a single element under control of a clock signal. Therefore, the invention can effectively reduce chip area, power consumption, and logic delay.