Dynamic Focus Exclusion Region for Lithography Yield
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Solution Overview
Problem
In semiconductor manufacturing, the current lithography processes face challenges in achieving precise focus and leveling control, particularly in the step-and-scan exposure system, where the focus control exclusion region is typically set as a circular shape, leading to insufficient focus-leveling control for chip areas near the wafer's periphery, resulting in a high yield of defective chips.
Innovation Solution
The focus control exclusion region is dynamically set based on the exposure map and chip layout, allowing for flexible boundaries that adjust according to the wafer's periphery, ensuring that chip areas within the effective region receive precise focus-leveling data for accurate exposure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a circular focus control exclusion region is used in step-and-scan exposure, then the exposure process is simplified, but focus-leveling control becomes insufficient for chip areas near the wafer periphery
Solution Approach 1:
The patent applies local quality by transitioning from a uniform circular exclusion region to a dynamically adjusted exclusion region that adapts to local chip layout characteristics. Different regions of the wafer receive differentiated focus control treatment based on their specific chip area locations, ensuring high-precision focus-leveling control where needed while maintaining process efficiency.
Solution Approach 2:
The patent implements dynamics by making the focus control exclusion region dynamic rather than static. The exclusion region is dynamically adjusted based on the specific exposure map and chip layout being processed, allowing the system to adapt its focus control strategy in real-time to match the actual manufacturing requirements of different chip arrangements.
2Device complexity
If the focus control exclusion region is fixed as circular, then device complexity is reduced, but the yield of good chips decreases due to insufficient focus control at wafer edges
Solution Approach 1:
The patent applies parameter changes by modifying the geometric parameters of the focus control exclusion region from a fixed circular shape to a dynamically adjustable shape. The exclusion region's boundaries are adjusted based on chip layout parameters, allowing the system to optimize focus control coverage for different chip arrangements and thereby improve chip yield without excessive complexity increase.
3Loss of time
If focus-leveling data is not used for chip areas in the exclusion region, then processing time is reduced, but manufacturing precision deteriorates for peripheral chip areas
Solution Approach 1:
The patent applies segmentation by dividing the wafer surface into different zones based on chip layout characteristics. The focus control exclusion region is segmented to exclude only those specific areas where focus control is not critical, while including peripheral chip areas that require precise focus control. This selective segmentation allows efficient processing time management while maintaining manufacturing precision where needed.
Data Source
AI summary
In a method executed in an exposure apparatus, a focus control effective region and a focus control exclusion region are set based on an exposure map and a chip area layout within an exposure area. Focus-leveling data are measured over a wafer. A photo resist layer on the wafer is exposed with an exposure light. When a chip area of a plurality of chip areas of the exposure area is located within an effective region of a wafer, the chip area is included in the focus control effective region, and when a part of or all of a chip area of the plurality of chip areas is located on or outside a periphery of the effective region of the wafer, the chip area is included in the focus control exclusion region In the exposing, a focus-leveling is controlled by using the focus-leveling data measured at the focus control effective region.