Dynamic FPGA Data Plane Architecture for Scalable Switching
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Solution Overview
Problem
Current data plane architectures for Ethernet switches and routers face challenges in scaling across various speeds and sizes without increasing costs, particularly in FPGA platforms, where high-speed operations require expensive hardware and inefficient memory usage for lookup tables.
Innovation Solution
A dynamic and flexible multi-processing dataplane architecture that adapts to different FPGA architectures by using multiple processing units, processing pipes, and various memory types, including DDR-SDRAM and BRAM, to manage ingress and egress data processes efficiently across multiple FPGAs, optimizing memory access and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a 1024 bit data bus is used to support 100 Gbps switch speed, then the switch capacity is improved, but the FPGA cost and device size increase significantly
Solution Approach 1:
The data bus is segmented into multiple smaller buses (e.g., 128-bit buses) that operate in parallel or sequentially. Instead of using a single 1024-bit bus, the system divides the bandwidth into manageable segments that can be handled by smaller, less expensive FPGA resources while achieving the same aggregate throughput through multiple channels.
Solution Approach 2:
The data bus width and configuration are made dynamic and adaptable. The system can adjust the bus width and number of buses based on the actual traffic requirements, allowing it to operate efficiently at lower speeds using smaller buses and only scaling to larger bus configurations when high-speed performance is actually needed, thus avoiding the cost of always having maximum capacity hardware.
2Productivity
If the operating frequency is increased to 250 MHz to support higher speeds, then the switch performance is improved, but it becomes difficult to meet timing requirements when utilization exceeds 70%
Solution Approach 1:
The processing workload is segmented across multiple processing elements or pipelines that can operate at lower, more manageable clock frequencies. By dividing the data flow into parallel processing streams, each operating at a relaxed timing regime, the system achieves high aggregate throughput without requiring any single element to operate at unsustainable high speeds with tight timing constraints.
Solution Approach 2:
Instead of processing all data at maximum speed through a single high-frequency path, the system uses multiple lower-frequency paths that collectively handle the full load. This distributes the timing pressure across multiple less-critical paths, making it easier to meet timing requirements while still achieving the necessary overall performance.
3Speed
If expensive memory types like CAM or QDR SRAM are used to store lookup tables, then the access speed is improved, but the product cost increases abysmally
Solution Approach 1:
Different types of memory are used in different locations within the system based on specific performance requirements. Critical lookup tables that require fast access are placed in high-speed memory (BRAM or block RAM), while less time-sensitive data resides in slower, cheaper DDR SDRAM. This localized optimization provides fast access where needed without paying for high-speed memory throughout the entire system.
Solution Approach 2:
The memory system uses a composite architecture combining multiple memory types (BRAM, block RAM, and DDR SDRAM) in a hierarchical structure. This composite memory system leverages the strengths of each memory type - the speed of BRAM for critical lookups and the capacity and cost-effectiveness of DDR SDRAM for larger databases - achieving an optimal balance between performance and cost.
4Device complexity
If normal DDR3 memory devices are used to store lookup tables, then the cost is reduced, but the random access delays become too large for effective operation
Solution Approach 1:
The most frequently accessed lookup table entries are cached in fast BRAM or block RAM located close to the processing logic, while the complete database resides in slower DDR SDRAM. This creates a local high-speed cache layer that eliminates random access delays for critical operations while maintaining the cost benefits of using DDR SDRAM for the bulk storage capacity.
Data Source
AI summary
A system and method for providing multi-processor data plane architecture have been provided. The method comprises selecting several processing units for performing an egress data process and an ingress data process. A number of processing units are selected for performing an egress data process based on a type of switch and data rate. Several processing pipes are provided for each processing unit. Each processing pipe is divided into several processing stages based on a number of lookup tables used in the egress data process and the ingress data process to absorb a response time of a memory device. The data is stored in several databases in each processing unit, and the databases are copied into several banks to increase an access time with a storage device, such as DDR-SDRAM. Several headers are resynchronized using a fixed delay time through an ACL unit.