Dynamic FPGA Logic Capacity via Early Routability Estimation
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Solution Overview
Problem
Designs for field programmable gate arrays (FPGAs) often face inefficiencies due to inadequate routing flexibility, leading to wasted resources and computing time, as architects struggle to balance routing flexibility with FPGA area usage, resulting in either underutilization of logic blocks or unnecessary area growth.
Innovation Solution
A computer-aided design (CAD) system that performs synthesis and generates early routability and logic usage estimations, allowing for dynamic adjustment of FPGA logic capacity based on design properties, enabling users to optimize logic block usage and routing flexibility, thereby reducing waste and improving resource utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If architects add more routing flexibility (muxing) to FPGA, then users can utilize more logic blocks, but the FPGA area grows needlessly
Solution Approach 1:
The patent applies dynamics by making the logic capacity of FPGA adjustable and reconfigurable based on actual design requirements. Instead of fixing the logic capacity upfront, the system dynamically determines the appropriate logic capacity after analyzing the specific design's routing needs, allowing the FPGA to adapt its resources to match the actual requirements rather than providing excessive fixed resources
Solution Approach 2:
The patent changes the parameter of logic capacity from a fixed value to a variable that can be adjusted based on design characteristics. By analyzing routing flexibility requirements and logic block usage patterns, the system modifies the effective logic capacity parameter to optimize the balance between routing capability and area utilization
2Area of stationary object
If architects add less routing flexibility (muxing) to FPGA, then the FPGA area is reduced, but users cannot utilize all logic blocks
Solution Approach 1:
The patent applies preliminary action by performing design analysis and routing requirement assessment before finalizing the FPGA configuration. The system预先 (in advance) determines the appropriate logic capacity and routing flexibility needed for the specific design, preventing both over-provisioning and under-provisioning of resources
Solution Approach 2:
The system uses feedback mechanisms to analyze design characteristics, evaluate routing requirements, and adjust logic capacity accordingly. By continuously assessing the relationship between logic block usage and routing needs, the system provides feedback to optimize the configuration balance
3Device complexity
If FPGA presents a fixed logic capacity to users, then the architecture is simple, but resources are either underutilized or wasted
Solution Approach 1:
The patent transforms the static logic capacity into a dynamic parameter that can be adjusted based on design requirements. This dynamic approach enables the system to optimize resource utilization for different designs without requiring complex manual configuration, achieving high productivity through automated adaptive resource allocation
Data Source
AI summary
A computer aided design (CAD) system receives a high level coding of a design for a circuit to be implemented in a field programmable gate array (FPGA). The system performs synthesis on the design, to produce a synthesized design. The system generates a routability estimation and a logic usage estimation for the synthesized design. The system determines whether the synthesized design is implementable on a specific FPGA, based on the routability estimation, the logic usage estimation, and available resources of the specific FPGA.