Dynamic Fragmented Address Space Layout Randomization for Code Security

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Solution Overview

Problem

Current Address Space Layout Randomization (ASLR) techniques are vulnerable to code-reuse attacks due to low entropy and coarse granularity, allowing attackers to deduce the location of code gadgets, which can be exploited for malicious purposes.

Innovation Solution

Dynamic Fragmented Address Space Layout Randomization (DFASLR) provides configurable granularity and true runtime code layout randomization, randomizing instruction locations down to the individual level, disrupting gadgets, detecting control-flow integrity attacks, and offering runtime patching and covert technique insertion.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional ASLR techniques are used with low entropy and coarse granularity, then the implementation is simpler and performance overhead is lower, but the security against code-reuse attacks is weakened

Engineering Contradiction:
Improvesecurity against code-reuse attacksVSAvoidASLR implementation complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the code into fine-grained fragments at the instruction level, allowing each fragment to be independently randomized. This segmentation enables high-entropy ASLR while maintaining manageable complexity through systematic fragment identification and relocation mechanisms

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic ASLR that operates at runtime rather than static compilation time. The code layout is continuously randomized during execution, creating a moving target that adapts to attack attempts. This dynamic approach enhances security without requiring complex pre-computed randomization schemes

Inventive Principle:
Principle #15Dynamics

2Reliability

If ASLR randomization is applied at finer granularity (instruction level), then the entropy and security strength are increased, but the performance overhead and execution time increase

Engineering Contradiction:
Improveentropy of code layout randomizationVSAvoidexecution performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent performs preliminary identification and classification of instructions into fixed and relocatable fragments during compilation or initialization. This pre-processing eliminates the need for complex analysis during runtime execution, reducing performance overhead while maintaining fine-grained randomization capability

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent applies different randomization strategies to different types of instructions. relocatable instructions are randomized while fixed instructions maintain their original positions, optimizing the balance between security entropy and execution performance by randomizing only where necessary

Inventive Principle:
Principle #3Local quality

3Reliability

If code is randomized at runtime, then the lifetime of discovered references is reduced and security is enhanced, but the complexity of maintaining code integrity and correctness increases

Engineering Contradiction:
Improvesecurity against side-channel attacksVSAvoidcode integrity maintenance complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements feedback mechanisms that monitor and detect code-reuse attack attempts. When attacks are detected, the system responds by re-randomizing the code layout or activating additional security measures. This feedback loop enhances security while managing complexity through targeted responses rather than continuous complex operations

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS11809871B2Dynamic fragmented address space layout randomization
Publication Date: 2023.11.07 RAYTHEON CO
  • US11809871B2 patent drawing
  • US11809871B2 patent drawing
  • US11809871B2 patent drawing

AI summary

A method can include identifying fixed instructions of the instructions and relocatable instructions of the instructions, the fixed instructions reference another instruction of the instructions and the relocatable instructions do not reference another instruction of the instructions, altering the location of the relocatable instructions relative to one another in the memory and add respective reference instructions to the fixed instructions and relocatable instructions that cause the instructions to be executed in a same order as they would be if the location was not altered, and executing the fixed instructions and the relocatable instructions from their altered locations in the medium.