Dynamic Frequency Scaling for JTAG Communication Integrity
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Solution Overview
Problem
Software testing is hindered by voltage fluctuations in the system under test (SUT) that render communications with the testing computer incompatible due to power-saving modes, where the SUT reduces voltage to levels incompatible with the high clock signal frequency used for communication.
Innovation Solution
Implementing control logic in the SUT that monitors the number of processors in a scan chain and dynamically adjusts the clock signal frequency to maintain communication integrity, reducing the frequency when processors are reduced and increasing it when more processors are active, thereby adapting to voltage fluctuations and ensuring communication compatibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the clock signal frequency is set at the highest possible value to maximize performance, then communication speed is improved, but compatibility with power-saving modes deteriorates because the SUT cannot sustain the high frequency at reduced voltage levels
Solution Approach 1:
The system dynamically adjusts the clock signal frequency based on the operational state of the SUT. When the SUT enters power-saving mode with reduced voltage, the frequency is automatically decreased to a level compatible with the reduced voltage. When the SUT operates at full voltage, the frequency can be increased to maximize communication speed. This dynamic adaptation resolves the contradiction between maintaining high speed and being compatible with power-saving modes.
Solution Approach 2:
The invention changes the frequency parameter of the clock signal in response to voltage level changes. By monitoring the voltage level or power-saving state and adjusting the frequency accordingly, the system maintains communication compatibility across different operating conditions. This parameter adjustment allows the system to operate reliably both in power-saving mode and in full-performance mode.
2Use of energy by moving object
If the voltage of the SUT is reduced to save power, then energy consumption is improved, but communication compatibility with the testing computer deteriorates due to incompatibility with the clock signal frequency
Solution Approach 1:
The system implements feedback by monitoring the voltage level or power-saving state of the SUT and using this information to adjust the clock signal frequency. This closed-loop control ensures that the frequency remains compatible with the current voltage level, maintaining communication reliability while allowing the SUT to operate at reduced voltage for energy savings.
Solution Approach 2:
The invention changes the frequency parameter dynamically in response to voltage changes. When voltage is reduced for energy savings, the frequency is automatically adjusted to a compatible level. This parameter adaptation ensures that communication reliability is maintained even when the SUT operates at lower voltage for reduced energy consumption.
3Loss of time
If the number of processors in the scan chain is reduced to improve testing efficiency, then testing time is improved, but communication stability deteriorates due to voltage fluctuations
Solution Approach 1:
The system dynamically adjusts the clock frequency based on the number of active processors in the scan chain. When fewer processors are active, the voltage and frequency are reduced accordingly, which improves communication stability by matching the frequency to the available processing capacity. This dynamic adjustment allows the system to efficiently handle varying numbers of processors without compromising communication stability.
Data Source
AI summary
A system comprising a system under test (SUT) having a control logic. The SUT further comprises testing logic coupled to the SUT and adapted to provide to the SUT a clock signal to facilitate communications between the testing logic and the SUT. The control logic monitors a number of activated processors in a scan chain coupled to the control logic. If the number of activated processors is reduced, the control logic dynamically decreases a frequency of the clock signal.