Dynamic FSBL Loading for SPI Flash Startup Speed
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Solution Overview
Problem
The existing method of loading a first-stage bootloader (FSBL) in embedded systems using SPI flash memory is too slow due to a low clock rate of the SPI controller in the Bootrom, which is not suitable for applications sensitive to startup time, such as PCIe cards, where initialization must be completed within 120 ms.
Innovation Solution
A method that involves loading a bin file at a first speed, adjusting the program loading speed to a second speed using configuration parameters in the bin file, and enabling Quad SPI mode to achieve a faster loading speed, reducing the FSBL loading time from 40 ms to 2.4 ms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the clock rate of the SPI controller in the Bootrom is kept low to ensure compatibility with various SPI Nor flash, then compatibility is improved, but the loading time of FSBL increases significantly
Solution Approach 1:
The patent applies dynamics by making the SPI controller clock rate adjustable rather than fixed. The system dynamically switches between a first clock rate (higher speed) for loading the FSBL and a second clock rate (lower speed) for subsequent operations, allowing both fast initial loading and sustained compatibility with various flash devices.
Solution Approach 2:
The patent applies preliminary action by loading the FSBL at a higher clock rate before the system needs to operate with various flash devices. The configuration parameter is read and processed in advance to prepare the optimal loading speed, so that the time-critical FSBL loading is completed quickly before compatibility mode is activated.
2Loss of time
If the clock rate is increased to reduce FSBL loading time, then loading speed is improved, but compatibility with various SPI Nor flash is compromised
Solution Approach 1:
The system dynamically adjusts the clock rate based on the operational phase: using a higher first clock rate during FSBL loading and switching to a lower second clock rate during normal operation with various flash devices. This dynamic adjustment resolves the contradiction between speed and compatibility.
Solution Approach 2:
The configuration parameter is read and processed in advance to determine the optimal loading speed before actual FSBL loading begins. This preliminary preparation allows the system to optimize loading speed without compromising subsequent compatibility.
3Adaptability or versatility
If a fixed low clock rate is used in the Bootrom, then compatibility is maintained, but the startup time becomes too long for time-sensitive applications
Solution Approach 1:
The patent transforms the fixed clock rate into a dynamic, adjustable parameter. The system uses a first clock rate for time-critical FSBL loading and switches to a second clock rate for compatible operation with various flash devices, thereby improving both startup time and compatibility.
Solution Approach 2:
The configuration parameter is processed in advance to prepare the optimal loading speed, enabling the system to achieve fast startup by loading FSBL at higher speed before compatibility mode is activated.
Data Source
AI summary
The disclosure relates to a method, apparatus, computer-readable medium and electronic device for program loading. The method includes: loading the bin file at a program loading speed that is a first speed, adjusting the program loading speed to a second speed based on the configuration parameter in the bin file, the second speed being faster than the first speed, and then loading a FSBL at the program loading speed that is the second speed. By executing the configuration parameter in the bin file to adjust the speed of the Bootrom loading the FSBL from flash memory, the time for the Bootrom to load FSBL is shortened, and thus embedded systems are enabled to be compatible with various flash memories while also being applicable in occasions sensitive to startup time.