Dynamic Gate-Drive LDOs for Selectable-Ratio Power Converters

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Solution Overview

Problem

Existing DC-DC power converter architectures face challenges such as excessive current in-rush during startup, charge imbalance leading to damaging voltage spikes, and the need for high efficiency in devices with constrained battery space, particularly in mobile electronics.

Innovation Solution

The implementation of low-dropout (LDO) power supplies that dynamically switch between voltage supply sources for power FETs, using internal voltage nodes to efficiently power lower-level power switches and limit current flow, thereby mitigating damaging events like current spikes during soft-starts and dynamic charge balancing without requiring additional circuitry.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If FET-based DC-DC power converter architecture is used, then high efficiency and flexibility are achieved, but excessive current in-rush occurs during startup

Engineering Contradiction:
Improvepower conversion efficiencyVSAvoidcurrent in-rush
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent applies preliminary action by implementing a soft-start mechanism that gradually enables the power converter. The control circuit progressively adjusts the duty cycle of the switch from zero to its target value, allowing capacitors to charge incrementally rather than all at once. This prevents the sudden current in-rush that would occur if the switch were immediately fully enabled, while still achieving the desired high efficiency once steady-state operation is reached.

Inventive Principle:
Principle #10Preliminary action

2Adaptability or versatility

If selectable conversion ratio is implemented, then flexibility for different power sources is improved, but circuit complexity increases

Engineering Contradiction:
Improveconversion ratio selectionVSAvoidcircuit architecture
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements universality by designing a single DC-DC power converter circuit that can operate in multiple conversion ratio modes (e.g., 1:1, 1:2, 1:3). The same basic circuit topology and components are used across all modes, with only the control signals and duty cycles being adjusted to change the conversion ratio. This eliminates the need for separate circuits for each conversion ratio, maintaining simplicity while providing flexibility for different power sources and voltage requirements.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If guard circuitry is added to prevent current in-rush, then reliability is improved, but device complexity increases

Engineering Contradiction:
Improveswitch protectionVSAvoidcircuit architecture
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies self-service by integrating the protection function directly into the existing control circuitry of the DC-DC converter. The control circuit that manages the switch duty cycle also inherently limits in-rush current through its soft-start implementation, eliminating the need for separate guard circuits. The same control signals that regulate normal operation also provide protection during startup and transient conditions, achieving reliability without adding complexity.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS12184174B2Reduced gate drive for power converter with dynamically switching ratio
Publication Date: 2024.12.31 MURATA MFG CO LTD
  • US12184174B2 patent drawing
  • US12184174B2 patent drawing
  • US12184174B2 patent drawing

AI summary

Circuits and methods for selectable conversion ratio power converters that include low-dropout (LDO) power supplies adapted to select voltage inputs based on the selected conversion ratio while achieving high efficiency. The LDO power supplies limit current through power FETs of power converters, thereby mitigating or eliminating potentially damaging events. In some embodiments, first and second full gate-drive LDOs have “wired-OR” outputs which may power a target circuit such as a pre-driver (and optionally, a level-shifter) coupled to the gate of a power FET. In some embodiments, first and second reduced gate-drive LDOs have “wired-OR” outputs that may power a final driver coupled to the gate of a power FET. Some embodiments have dual full gate-drive LDOs that power a target circuit such as a pre-driver (and optionally, a level-shifter), while dual reduced gate-drive LDOs that power a final driver coupled to the gate of the power FET.