Dynamic Guard Bit Adjustment in Arithmetic Unit Chains
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Solution Overview
Problem
In chains of arithmetic units performing reduced precision operations, guard bits are limited, leading to overflow issues that restrict the length of the chain and slow down computations, especially in applications like neural networks that require large chains, as resetting guard bits can take several clock cycles.
Innovation Solution
Implementing side-band logic to monitor and adjust guard bits dynamically by generating offset values to prevent overflow, allowing chains of arbitrary length without interrupting the computation, and using a guard corrector to generate reduced-precision results from the final multi-result vector.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If guard bits are allocated in the output vector to prevent overflow, then the reliability of arithmetic operations is improved, but the device complexity increases and the computation speed decreases due to the need to reset guard bits
Solution Approach 1:
The patent makes the guard bits dynamic by allowing them to be adjusted in real-time based on the actual needs of parallel operations. Instead of being fixed, the number of guard bits can be increased or decreased dynamically to match the overflow risk level, thereby maintaining reliability while optimizing computation speed.
Solution Approach 2:
The patent changes the parameter of guard bit allocation from a static fixed value to a dynamic value that adjusts based on operational requirements. By monitoring the parallel operations and adjusting guard bit allocation accordingly, the system maintains overflow prevention while reducing unnecessary computational overhead when less protection is needed.
2Productivity
If the chain of arithmetic units is extended to perform more parallel operations, then the productivity is improved, but the guard bits may overflow into adjacent operation results, worsening the reliability
Solution Approach 1:
The patent applies dynamics by making the guard bit allocation adaptive to the chain length and operation type. As the arithmetic unit chain extends, the system dynamically adjusts the number of guard bits needed for each operation based on the specific parallel operations being performed, ensuring reliability is maintained regardless of chain length.
Solution Approach 2:
The patent segments the output vector into multiple sub-portions, each dedicated to a specific parallel operation with its own allocated guard bits. This segmentation isolates potential overflow effects to specific segments, preventing them from affecting other operations in the chain, thereby maintaining reliability across extended chains.
3Reliability
If fixed guard bits are used to buffer overflow, then the reliability is improved, but the device complexity increases due to the need for guard monitoring and offset adjustment logic
Solution Approach 1:
The patent implements self-service by enabling the arithmetic units to automatically monitor and adjust their own guard bits without requiring external control logic. Each arithmetic unit independently manages its guard bit allocation based on the operations it performs, eliminating the need for complex external guard monitoring and offset adjustment circuits.
Solution Approach 2:
The patent introduces feedback mechanisms where the results of parallel operations are monitored to detect potential overflow conditions, and this information is fed back to dynamically adjust guard bit allocation in real-time. This feedback loop maintains reliability while keeping the control logic simple and integrated within the arithmetic units themselves.
Data Source
AI summary
The embodiments herein describe techniques for monitoring guard bits in multi-result vectors generated by a first arithmetic unit in a chain and using side band logic to add or subtract offset values from guard bits in a second, subsequent arithmetic unit in the chain. In this manner, the guard bits can be adjusted on the fly (e.g., without interrupting or terminating the chain) to ensure the guard bits do not overflow. The side band logic can maintain a guard bits overflow value which is then combined with the output vector from the final arithmetic unit in the chain to compensate for adjusting the guard bits at the various arithmetic units in the chain. In this manner, the chain can have any desired length.