Dynamic Host Interface Speed Adjustment in Storage Arrays

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Solution Overview

Problem

Conventional storage arrays consume excessive power due to fixed host interface signaling speeds, which do not adapt to varying application loads, leading to inefficiencies in power usage and bandwidth utilization.

Innovation Solution

A system comprising an interface circuit and controller that dynamically adjusts host interface signaling speeds based on data traffic, application load, and performance thresholds, allowing for power-efficient operation by switching between supported speeds and entering low power modes when necessary.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the host interface signals at the fastest supported speed, then the bandwidth capability is maximized, but the power consumption increases significantly

Engineering Contradiction:
Improvehost interface signaling speedVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The host interface signaling speed is made dynamic rather than fixed. The system continuously monitors application load and data traffic patterns, then adjusts the signaling speed accordingly. When load is low, the interface operates at slower speeds to reduce power consumption. When load increases, the speed is increased to maintain performance, thus resolving the contradiction between speed and power consumption.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the operational parameter of signaling speed based on monitored conditions. By varying the speed parameter from fastest to slower speeds depending on application requirements, the system achieves both high performance when needed and low power consumption when not needed, resolving the technical contradiction.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If the host interface signals at the fastest supported speed, then the raw bandwidth is maximized, but the power bandwidth ratio deteriorates

Engineering Contradiction:
Improveraw bandwidthVSAvoidpower bandwidth ratio
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The system implements feedback mechanisms that monitor application load and data traffic patterns. This feedback information is used to dynamically adjust the signaling speed, ensuring that the interface operates at the minimum necessary speed to meet performance requirements. This feedback-driven adjustment optimizes the power bandwidth ratio by avoiding excessive power consumption when full bandwidth is not required.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

Instead of always operating at full speed (excessive action), the system applies partial action by operating at reduced speeds when the application load does not require full bandwidth. This partial operation reduces power consumption while maintaining adequate performance, thereby improving the power bandwidth ratio.

Inventive Principle:
Principle #16Partial or excessive action

3Use of energy by moving object

If the interface speed is reduced to save power, then power consumption decreases, but the data transfer performance may be degraded

Engineering Contradiction:
Improvepower consumptionVSAvoiddata transfer performance
Core Design Contradiction:
Use of energy by moving objectVSProductivity

Solution Approach 1:

The interface speed is dynamically adjusted based on real-time monitoring of application load and data traffic patterns. The system transitions between different speed levels smoothly, ensuring that performance is maintained when needed while power is saved when not needed. This dynamic adjustment resolves the contradiction by making speed a flexible parameter rather than a fixed one.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system performs preliminary monitoring and analysis of data traffic patterns to predict when performance requirements will be met. By proactively adjusting speed based on anticipated load conditions, the system prevents performance degradation before it occurs, while still achieving power savings during low-load periods.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8473645B2Varying host interface signaling speeds in a storage array
Publication Date: 2013.06.25 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • US8473645B2 patent drawing
  • US8473645B2 patent drawing
  • US8473645B2 patent drawing

AI summary

An apparatus comprising an interface circuit and a controller. The interface circuit may be configured to calculate a speed signal in response to data traffic measured over a network. The controller may be configured to present and receive data from an array in response to (a) the speed signal and (b) one or more input/output requests. The interface circuit may generate the speed signal in response to a plurality of predetermined factors. The controller may present and receive the data at one of a plurality of speeds in response to the speed signal.