Dynamic Hybridized Positional Notation Instruction Set Architecture
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Solution Overview
Problem
Conventional computing systems have a fixed architecture and instruction set, making them vulnerable to malicious code exploits, such as buffer overflow attacks, as attackers can generate valid machine code executable by the system if they know its architecture and instruction set.
Innovation Solution
A dynamic hybridized positional notation instruction set computer architecture that includes multiple processing units capable of executing instructions in different numerical bases (binary, trinary, quaternary, etc.), dynamically changing its configuration to execute different machine code instruction sets, and using a multicompiler to compile instructions for each unit, ensuring that an attacker cannot generate valid machine code in the current system state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed architecture and instruction set are used, then the system is simple to implement and operate, but it becomes vulnerable to malicious code exploits
Solution Approach 1:
The patent implements a dynamic instruction set architecture where the system can switch between different numerical bases (binary, trinary, quaternary, etc.) at runtime. The processing unit changes its operational state by adopting different positional notation systems, making the architecture fluid rather than fixed. This dynamic transformation allows the system to adapt its instruction set according to security requirements while maintaining operational simplicity through automated base conversion.
Solution Approach 2:
The core mechanism involves changing the numerical base parameter of the instruction set. By varying the base (2, 3, 4, 5, etc.), the system fundamentally alters its operational characteristics and instruction encoding. This parameter change approach allows the same hardware to support multiple instruction sets without physical reconfiguration, enhancing security while avoiding the complexity of multiple dedicated architectures.
2Reliability
If multiple processing units with different instruction sets are implemented, then security is enhanced, but device complexity increases
Solution Approach 1:
The patent creates a universal processing unit capable of functioning in multiple numerical bases. Rather than implementing separate processing units for binary, trinary, and quaternary systems, a single unit is designed to dynamically adopt any base. This multi-functional approach consolidates what would otherwise require multiple dedicated units, reducing hardware complexity while maintaining the security benefits of diverse instruction sets.
Solution Approach 2:
The instruction set is segmented into different numerical base representations, with each base providing a distinct operational mode. The processing unit divides its functionality across these segments, switching between them as needed. This segmentation allows the system to present multiple instruction set interfaces through a single unified hardware structure, avoiding the complexity of physically integrating multiple complete processing units.
3Reliability
If dynamic architecture changing is implemented, then attackers cannot generate valid machine code, but the system requires complex compilation mechanisms
Solution Approach 1:
The patent introduces a compiler as an intermediary layer between the high-level programming language and the dynamic instruction set. The compiler translates source code into the appropriate numerical base representation based on the current system state. This intermediary handles the complexity of base conversion and instruction generation, shielding the user from complexity while enabling secure dynamic operation. The compiler acts as a mediator that adapts the static source code to the dynamic target architecture.
Solution Approach 2:
The compilation process performs preliminary action by pre-translating high-level code into multiple numerical base representations. Rather than converting at runtime, the compiler prepares the instructions in advance for different bases, allowing the processing unit to simply switch between pre-compiled instruction sets. This preliminary compilation reduces runtime complexity while maintaining the security advantages of dynamic architecture changing.
Data Source
AI summary
Disclosed herein is a computing system with the capability to execute instructions in different positional notation values. The definition of a positional notation value is given by the general formula that represent a base 10 numeral in any positional notation in the following manner: . . . d3r3+d2r2+d1r1+d0r0, where d is a coefficient, r is the base of the positional number system (i.e. r=2 for binary, or r=3 for ternary), and the exponent is the position of the digit. The computing may provide a configuration which hybridizes the instructions of multiple positional notation values in variable ratios. The computing system may dynamically switch between the multiple hybridized instructions sets. Embodiments may be applied to provide security benefits.