Dynamic Image Processing Blocks for Parallel Video Analysis

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Solution Overview

Problem

Existing digital video processing systems use separate, fixed image processing blocks that lead to redundancy, increased cost, reduced image quality, and processing inefficiencies due to sequential processing and potential mismatch in processing enhancements between stages.

Innovation Solution

A dynamic image processing system that uses dynamically controllable processing blocks, where classification and processing tag data are used to adjust processing operations in real-time, allowing for granular control of de-interlacing, interpolation, and other image processing tasks based on changing pixel characteristics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If separate and independent fixed image processing blocks are used for de-interlacing, scaling, and other processing functions, then each processing stage can be implemented with dedicated hardware, but this results in increased redundancy, increased cost, and reduced processing efficiency

Engineering Contradiction:
Improveprocessing stabilityVSAvoidsystem redundancy
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements a universal image processing block that can dynamically perform multiple processing functions (de-interlacing, scaling, noise reduction, sharpening) through reconfigurable logic controlled by classification tag data. This single multi-functional block replaces what would traditionally require multiple separate dedicated processing blocks, thereby reducing system redundancy and cost while maintaining processing stability through dedicated hardware implementation.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent employs dynamically reconfigurable processing blocks that can change their processing mode and parameters in real-time based on classification tag data generated from pixel analysis. This dynamic adaptability allows the same hardware block to optimize its function for different image regions and processing requirements, eliminating the need for multiple fixed processing blocks and reducing overall system complexity.

Inventive Principle:
Principle #15Dynamics

2Reliability

If sequential processing flow is used through multiple processing stages, then each processing operation can be completed in order, but this prevents additional targeted processing and reduces processing efficiency

Engineering Contradiction:
Improveprocessing completionVSAvoidprocessing efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent divides the image into multiple regions based on classification tag data (e.g., motion regions, static regions, edge regions, smooth regions) and applies different processing operations to different segments simultaneously. This segmentation enables parallel processing of different image regions with different processing requirements, dramatically improving processing efficiency while ensuring each region receives appropriate processing completion.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent adds a spatial dimension to processing by applying different processing operations to different spatial regions of the image simultaneously. Instead of processing the entire image through a single sequential pipeline, the system processes multiple regions in parallel with region-specific operations, transforming the processing architecture from one-dimensional sequential to multi-dimensional parallel processing.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Device complexity

If pixel data is passed between processing stages without additional tag data, then the processing pipeline remains simple, but processing enhancements from one stage can be counteracted by later processing and error magnification can occur

Engineering Contradiction:
Improvedata structure simplicityVSAvoidimage quality consistency
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The patent implements a feedback mechanism where classification tag data generated from pixel analysis is fed forward to subsequent processing blocks to guide their processing operations. This feedback loop ensures that processing enhancements are maintained and coordinated across different processing stages, preventing counteracting effects and error magnification while preserving data structure simplicity through efficient tag data passing.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent introduces classification tag data as an intermediary between processing stages. These tags carry information about pixel characteristics (motion, edge, noise levels) that mediate the processing operations at each stage, ensuring consistency and coordination without requiring complex data structures. The tags act as a lightweight communication mechanism that maintains image quality consistency across the processing pipeline.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS9292904B2Video image processing with parallel processing
Publication Date: 2016.03.22 NVIDIA CORP
  • US9292904B2 patent drawing
  • US9292904B2 patent drawing
  • US9292904B2 patent drawing

AI summary

This document discusses systems and methods that track overall time for processing operations such that the processing time can be shared among the resources efficiently. Processing time can be shifted to image processing to provide the most benefit to image quality. Moreover, access time from one process is banked to be used by a subsequent process or on a subsequent group of pixels. This document discusses systems and methods that provide additional processing power on an as needed basis. For example, a processing stage and its controller are outside the normal pixel processing flow path. When it is determined that additional processing is required, the processing stage and its controller are activated to perform the additional processing. This document discusses systems and methods that provide parallel processing in a processing stage such that the data can flow internal to the controller linked to the processing stage and globally.