Dynamic Ingress Buffer Credit Allocation for Packet Switch Throughput

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Solution Overview

Problem

The throughput of packet switches, particularly those compliant with the PCIe 2.0 standard, is often suboptimal due to insufficient storage capacity in ingress buffers, leading to inefficient routing and resource allocation among different transaction types.

Innovation Solution

A packet switch design that allocates storage capacity dynamically among transaction types using credits in random access memory, eliminating the need for dedicated buffers for each transaction type, thereby optimizing resource utilization and increasing throughput.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If dedicated ingress buffers are allocated for each transaction type, then reliability of packet routing is improved, but device complexity and die area increase

Engineering Contradiction:

Improvepacket routing reliabilityVSAvoidbuffer structure complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges multiple dedicated buffers for different transaction types (posted, non-posted, completion packets) into a single shared ingress buffer. The buffer is divided into multiple regions that can dynamically serve different transaction types based on current traffic patterns, eliminating the need for separate physical buffers while maintaining reliable packet routing for all transaction types.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The ingress buffer is designed as a universal structure that can handle multiple transaction types through a single buffer interface. The buffer regions are configured to serve different packet types as needed, making the buffer multi-functional rather than dedicated to a single transaction type, thus reducing complexity while preserving reliability.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Productivity

If larger storage capacity is allocated to ingress buffers, then throughput is improved, but die area and power consumption increase

Engineering Contradiction:

Improvepacket switch throughputVSAvoiddie area

Core Design Contradiction:

ProductivityVSArea of stationary object

Solution Approach 1:

The patent implements dynamic allocation of buffer regions where the storage capacity assigned to each transaction type can change based on real-time traffic patterns. The ingress controller monitors packet types and dynamically adjusts the size and availability of buffer regions, allowing the system to achieve high throughput only when needed for specific transaction types rather than maintaining large static buffers for all types simultaneously.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The system changes the parameters of buffer allocation by dynamically adjusting the storage capacity assigned to different transaction types. The ingress controller modifies buffer region sizes and credit allocations based on observed traffic patterns, enabling the system to optimize throughput for current workloads while minimizing the total die area required compared to fixed large buffers.

Inventive Principle:

Principle #35Parameter changes

3Adaptability or versatility

If multiple dedicated buffers are used for different packet types, then adaptability to various transaction types is improved, but device complexity increases

Engineering Contradiction:

Improvetransaction type adaptabilityVSAvoidbuffer management complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent segments the single ingress buffer into multiple logical regions that can be independently configured for different transaction types. Each region can be dynamically assigned to handle specific packet types (posted, non-posted, completion packets) as needed. This segmentation provides adaptability to various transaction types while maintaining a unified buffer structure that is simpler than multiple dedicated buffers.

Inventive Principle:

Principle #1Segmentation

4Ease of manufacture

If fixed storage capacity is allocated to ingress buffers, then ease of manufacture is improved, but throughput for different applications deteriorates

Engineering Contradiction:

Improvebuffer design simplicityVSAvoidapplication-specific throughput

Core Design Contradiction:

Ease of manufactureVSProductivity

Solution Approach 1:

The patent transforms the fixed buffer allocation design into a dynamic one where the ingress controller adjusts buffer region sizes and credit allocations based on observed traffic patterns. The buffer structure remains manufacturable with fixed physical boundaries, but the logical allocation of storage capacity to different transaction types changes dynamically, enabling optimized throughput for various applications without sacrificing manufacturing simplicity.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS8391302B1High-performance ingress buffer for a packet switch

Publication Date: 2013.03.05 MICROSEMI STORAGE SOLUTIONS US INC

AI summary

A packet switch includes ingress ports, each of which contains a random access memory having a storage capacity for storing data. An ingress controller of the packet switch allocates the storage capacity of each random access memory among transaction types of packets by allocating credits to each of the transactions types for the random access memory. Each ingress port accepts packets based on the transaction types of the packets and the credits of the random access memory in the ingress port. Moreover, the ingress port stores accepted packets in the random access memory of the ingress port. In further embodiments, the ingress controller dynamically reallocates the credits of the random access memory in the ingress port during operation of the packet switch.