Dynamic Inhibit Voltage Boosting for NAND Flash Program Disturb Reduction
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Solution Overview
Problem
As NAND flash memory scales down, the dominant pattern of bit lines adjacent to inhibited bit lines during programming (CS2 pattern) increases raw bit error rates due to channel voltage loss between CS2 and CS0 patterns, leading to disturb errors in low program voltage regions.
Innovation Solution
Implementing different channel voltage boosting schemes, such as varying inhibit voltage waveforms and boosting inhibit voltages during low program voltage portions, to compensate for channel voltage loss in regions with a CS2 pattern, and shifting back to traditional inhibit pulses when a CS0 pattern dominates, thereby reducing disturb errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional inhibit pulses are used during programming, then device complexity is reduced, but raw bit error rates increase due to channel voltage loss in CS2 pattern regions
Solution Approach 1:
The patent implements dynamic inhibit voltage waveforms that adapt during the programming sequence. The inhibit voltage is initially boosted above traditional levels during early programming pulses when CS2 patterns dominate, then transitions to traditional levels later when CS0 patterns dominate. This dynamic adjustment resolves the contradiction by maintaining reliability during critical low-voltage regions without permanently increasing device complexity.
Solution Approach 2:
The patent changes the voltage parameter of inhibit pulses during programming. By applying boosted inhibit voltages during early programming stages and transitioning to traditional voltages later, the system addresses channel voltage loss in CS2 regions without requiring fundamentally new circuitry. This parameter modification resolves the contradiction between simple control and high reliability.
2Reliability
If channel voltage is boosted during low program voltage portions, then disturb errors are reduced, but energy consumption increases
Solution Approach 1:
The patent applies boosted inhibit voltages periodically during specific phases of the programming sequence rather than continuously. The boosted voltage is applied during early programming pulses when CS2 patterns cause channel voltage loss, then transitions to traditional voltages later. This periodic application reduces disturb errors during critical periods while minimizing overall energy consumption compared to continuous boosting.
Solution Approach 2:
The patent segments the programming sequence into distinct phases with different voltage strategies. Early programming pulses receive boosted inhibit voltages to prevent disturb errors in CS2 regions, while later pulses use traditional voltages. This segmentation allows targeted energy expenditure only where and when needed, resolving the contradiction between reliability and energy consumption.
3Reliability
If different inhibit voltage waveforms are applied for CS2 and CS0 patterns, then error reduction is optimized, but device complexity increases
Solution Approach 1:
The patent uses dynamic waveform selection based on programming phase rather than requiring separate dedicated circuitry for CS2 and CS0 patterns. A control mechanism selects between boosted and traditional inhibit waveforms based on the current programming pulse sequence phase. This dynamic approach optimizes error reduction for both pattern types while avoiding the complexity of completely separate control paths.
Solution Approach 2:
The patent implements a universal inhibit voltage generation mechanism that can produce both boosted and traditional waveforms using the same hardware infrastructure. The control logic adapts the waveform characteristics based on programming needs, allowing one circuit to serve multiple functions. This multi-functionality resolves the contradiction by achieving pattern-specific optimization without proportionally increasing device complexity.
Data Source
AI summary
Methods of programming a memory include applying a programming voltage on an access line selected for a programming operation of a single page of the memory, applying a second voltage on an access line unselected for the programming operation, increasing the programming voltage for a first plurality of steps of the programming operation, and increasing the second voltage for a second plurality of steps of a first portion of the programming operation, then decreasing the second voltage at a particular point of the programming operation after completing the second plurality of steps and before completing the first plurality of steps.