Dynamic Inhibit Voltage for RRAM Write Power Reduction
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Solution Overview
Problem
Existing memory systems face challenges in efficiently writing to Resistive Random Access Memory (RRAM) cells due to process variations and defects, which can lead to increased gate stress, leakage, and power consumption.
Innovation Solution
The implementation of a dynamic inhibit voltage that adjusts according to different word line (WL) levels, coupled with a tracking circuit that monitors leakage over process, voltage supply voltage, and temperature (PVT) conditions, to optimize the write operation and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed inhibit voltage is provided to unselected memory cells, then the select transistors are protected from gate stress, but array leakage increases and write power consumption increases
Solution Approach 1:
The patent implements a dynamic inhibit voltage that changes according to different word line voltage levels. The tracking circuit generates inhibit voltages that are proportional to the word line voltage, allowing the inhibit voltage to adapt dynamically rather than remaining fixed. This resolves the contradiction by adjusting the inhibit voltage level to match operational requirements, protecting transistors when needed while minimizing leakage when word line voltage is lower.
Solution Approach 2:
The patent changes the parameter of inhibit voltage from a fixed value to a variable value that depends on word line voltage level. The tracking circuit monitors word line voltage and adjusts the inhibit voltage proportionally. This parameter change allows the system to optimize between transistor protection and leakage reduction by adapting the inhibit voltage to current operational conditions.
2Reliability
If a higher fixed inhibit voltage is provided to protect select transistors, then gate stress is reduced, but write power consumption increases due to higher array leakage
Solution Approach 1:
The dynamic inhibit voltage tracking circuit adjusts the inhibit voltage level based on the actual word line voltage being applied. When word line voltage is high, the inhibit voltage is proportionally higher to protect against gate stress. When word line voltage is lower, the inhibit voltage is reduced to minimize array leakage and write power consumption. This dynamic adjustment resolves the contradiction between protection and power consumption.
Solution Approach 2:
The tracking circuit implements a feedback mechanism where the inhibit voltage is generated based on monitoring of the word line voltage level. The circuit continuously adjusts the inhibit voltage in response to changes in word line voltage, ensuring optimal protection while minimizing power consumption. This feedback loop resolves the contradiction by adapting protection levels to actual operational needs rather than applying a constant high voltage.
Data Source
AI summary
In some aspects of the present disclosure, a memory device is disclosed. In some aspects, the memory device includes a first voltage regulator to receive a word line voltage provided to a memory array; a resistor network coupled to the first voltage regulator to provide an inhibit voltage to the memory array, wherein the resistor network comprises a plurality of resistors and wherein each of the resistors are coupled in series to an adjacent one of the plurality of resistors; and a switch network comprising a plurality of switches, wherein each of the switches are coupled to a corresponding one of the plurality of resistors and to the memory array via a second voltage regulator.