Dynamic Integrator Output-Impedance Boost for Fast Pipelined ADCs
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Solution Overview
Problem
As bandwidths and speeds of analog-to-digital converter (ADC) operations increase, the time available for integration decreases, leading to increased power consumption, and the sampling switch at the output of a dynamic integrator degrades performance.
Innovation Solution
A pipelined ADC circuit with a residue stage featuring a dynamic integrator configured to provide transconductance and boost the output impedance, utilizing a conductance boost circuit with differential transistors and switch arrangements to achieve high gain with low power consumption and reduced sensitivity to clock jitter.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If bandwidth and speed of ADC operations are increased, then conversion speed is improved, but power consumption increases and integration time decreases
Solution Approach 1:
The patent employs dynamic element sizing where transistor widths are adjusted based on operating conditions. The conductance boost circuit dynamically activates to increase output impedance only when needed, allowing the integrator to achieve required gain in shorter times without continuously consuming high power. This dynamic adaptation resolves the contradiction between speed and power consumption.
Solution Approach 2:
The patent changes the output impedance parameter of the transconductance stage by activating the conductance boost circuit. This parameter change allows the integrator to achieve higher gain in reduced integration time, thereby supporting higher ADC operating speeds without proportionally increasing power consumption throughout the entire operation cycle.
2Speed
If integration time is decreased to increase ADC speed, then conversion speed is improved, but gain achievement becomes more difficult and power consumption increases
Solution Approach 1:
The patent dynamically changes the output impedance parameter of the integrator by activating the conductance boost circuit during specific phases. This parameter modification enables the integrator to achieve the required gain even with reduced integration time, maintaining reliability while supporting higher conversion speeds.
Solution Approach 2:
The conductance boost circuit is activated in advance during specific integration phases to pre-establish the necessary output impedance level. This preliminary action ensures that when the integration window is shortened for higher speed operation, the gain requirement is still met because the boost circuit was already active to provide the necessary impedance enhancement.
3Ease of operation
If a sampling switch is added at the output of the dynamic integrator, then signal sampling capability is improved, but integrator performance is degraded
Solution Approach 1:
The patent extracts or removes the output sampling switch from the integrator circuit entirely. Instead of adding a sampling switch at the integrator output, the design uses the dynamic nature of the integrator itself and the conductance boost circuit to achieve the necessary signal capture functionality without the performance-degrading switch, thus maintaining integrator performance while preserving sampling capability.
Data Source
AI summary
A pipelined analog-to-digital converter (ADC) circuit includes a first ADC stage and a residue stage coupled to the first ADC stage. The residue stage includes a dynamic integrator configured to provide transconductance, wherein the dynamic integrator includes a boost circuit configured to boost an output impedance of the transconductance.