Dynamic Interrupt Mapping for VCPU Load Balancing

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Solution Overview

Problem

In virtual machine interrupt processing, existing technologies fail to consider the current scheduling states of Virtual CPUs (VCPUs) when mapping interrupts, leading to increased response delays and reduced processing rates due to inefficient allocation of interrupt requests.

Innovation Solution

A method for dynamic interrupt balanced mapping that analyzes the scheduling states and interrupt processing loads of VCPUs, allowing interrupts to be mapped into active VCPUs with the lowest current load, thereby reducing processing delays and balancing loads across VCPUs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If interrupts are mapped to VCPUs without considering scheduling states, then interrupt mapping is simple, but interrupt response delay increases

Engineering Contradiction:
Improveinterrupt response delayVSAvoidinterrupt mapping complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The system pre-establishes interrupt mapping relationships between VIOAPICs and VCPUs, and maintains scheduling state information of VCPUs in advance. When an interrupt occurs, the pre-collected scheduling state data is immediately queried to determine the target VCPU, avoiding real-time scheduling decisions and reducing interrupt response delay while managing complexity through advance preparation

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces an interrupt mapping mechanism that acts as an intermediary layer between the VIOAPIC and VCPUs. This intermediary considers VCPU scheduling states (such as whether the VCPU is in running, waiting, or blocked state) when routing interrupts, selecting appropriate target VCPUs based on their current states rather than using direct or round-robin mapping, thereby reducing interrupt response delay while managing complexity through the intermediary layer

Inventive Principle:
Principle #24Intermediary (Mediator)

2Loss of time

If context switch frequency is increased to reduce scheduling delay, then interrupt response improves, but CPU computing capability is wasted

Engineering Contradiction:
Improvescheduling delayVSAvoidCPU computing capability waste
Core Design Contradiction:
Loss of timeVSLoss of energy

Solution Approach 1:

The system dynamically selects the target VCPU for interrupt handling based on real-time scheduling states of available VCPUs. Instead of using fixed time slicing or increasing context switch frequency, the interrupt mapping mechanism adapts to the current runtime state of VCPUs (running, waiting, blocked), selecting the most appropriate target VCPU for each interrupt. This dynamic approach reduces scheduling delay without forcing unnecessary context switches, thereby avoiding waste of CPU computing capability

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS9697041B2Method for dynamic interrupt balanced mapping based on current scheduling states of VCPUs
Publication Date: 2017.07.04 SHANGHAI JIAOTONG UNIV
  • US9697041B2 patent drawing
  • US9697041B2 patent drawing
  • US9697041B2 patent drawing

AI summary

The invention discloses a method for dynamic interrupt balanced mapping method based on the current scheduling states of VCPUs. When the virtual I/O APIC of an SMP virtual machine needs to map a virtual interrupt into a VCPU of the virtual machine after receiving the virtual interrupt, a part of VCPUs in the active state are analyzed according to the scheduling states of all VCPUs of the current VM in a VMM scheduler, and the virtual interrupt is mapped into the active VCPUs to obtain lower interrupt processing delay. If a plurality of VCPUs are in the active state simultaneously, the interrupt load of each active VCPU is considered further, and the interrupt is mapped into the active VCPU with the current lowest current load to further ensure balancing of interrupt processing loads of all VCPUs, and therefore, the loads of VCPUs in the SPMP structure are more symmetrical to promote balancing of the overall performance of all VCPUs in the SMP structure.