Dynamic Interrupt Priority Adjustment for Multi-Core Resource Conflicts

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Solution Overview

Problem

Multiple core processors face delays due to resource conflicts when cores attempt to access shared resources simultaneously, and assigning priorities can lead to some tasks being significantly delayed or not executed at all.

Innovation Solution

Implementing task timers that adjust interrupt priority levels based on task duration, using a tidemark and timeout system to dynamically manage access to shared resources, ensuring that tasks are completed before timeouts occur by adjusting interrupt priority levels accordingly.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If priorities are assigned to processor cores to manage resource access, then access order is established and resource conflicts are reduced, but low priority cores may be denied access and tasks are significantly delayed or not executed

Engineering Contradiction:
Improveresource access efficiencyVSAvoidtask execution guarantee
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The interrupt priority level is made dynamic rather than static. The system monitors task execution time against predefined timeout values and automatically adjusts priority levels based on real-time performance. Tasks that exceed their timeout threshold have their interrupt priority level reduced, allowing the system to adapt priority assignments dynamically to ensure all tasks can complete within their time constraints.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system implements a feedback mechanism where task execution time is continuously monitored and compared against timeout values. Based on this feedback, the interrupt priority level is automatically adjusted. This closed-loop control ensures that tasks which are taking too long to execute will have their priority reduced, preventing permanent denial of access and ensuring reliable task completion.

Inventive Principle:
Principle #23Feedback

2Ease of operation

If fixed interrupt priority levels are assigned to all tasks, then resource access is simplified and predictable, but tasks with longer execution times cannot complete before timeout

Engineering Contradiction:
Improvepriority management simplicityVSAvoidtask execution time
Core Design Contradiction:
Ease of operationVSLoss of time

Solution Approach 1:

The system transitions from static fixed priorities to dynamic priorities that automatically adjust based on task execution progress. By monitoring elapsed time against timeout values and adjusting priority levels accordingly, the system maintains simplicity in operation while enabling tasks to complete within their time constraints.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The interrupt priority level parameter is changed dynamically based on task execution time. When a task exceeds its timeout threshold, the priority level parameter is modified to reduce the task's access rights. This parameter change allows the system to maintain simple priority management while preventing time loss.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10031771B2Multiple processor core interrupt priority levels
Publication Date: 2018.07.24 NXP USA INC
  • US10031771B2 patent drawing
  • US10031771B2 patent drawing
  • US10031771B2 patent drawing

AI summary

A processor system includes at least two processor cores and an interrupt controller including interrupt priority registers configured for registering interrupt priorities of the respective processor cores. The processor system further includes at least two task timers associated with respective processor cores. Each task timer includes a counter configured for producing a counter value, a timeout value register configured for storing a timeout value and a tidemark value register configured for storing a tidemark value smaller than the timeout value. Each task timer is configured for producing a timeout signal when the counter value equals the timeout value and for producing a tidemark signal when the counter value equals the tidemark value. The interrupt controller is configured for increasing the interrupt priority of a processor core in response to a tidemark signal and for decreasing the interrupt priority of a processor core in response to a timeout signal.