Dynamic Interrupt Rate Control for Power Management

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Solution Overview

Problem

Modern computing devices face a challenge in balancing power consumption and performance, as immediate handling of interrupts to maintain user experience increases power consumption, leading to reduced effectiveness of idle states in reducing power consumption.

Innovation Solution

Implementing a system that masks and delays servicing of interrupts based on their type and the current power-performance state, allowing coalescence of interrupts during idle periods, which are then serviced when the system transitions to a higher power state or upon receipt of a non-maskable interrupt.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If interrupts are handled immediately as they come in, then performance is improved, but power consumption increases

Engineering Contradiction:
ImproveperformanceVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The system performs preliminary classification of interrupts into maskable and non-maskable categories before processing. By anticipating which interrupts can be delayed and which cannot, the system prepares in advance to extend idle states safely, reducing unnecessary transitions from idle to active states and thereby lowering power consumption while maintaining responsive performance for critical interrupts.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system dynamically adjusts interrupt handling behavior based on current system state. During idle periods, maskable interrupts are delayed to maintain the low-power idle state. When activity is detected or non-maskable interrupts occur, the system transitions to active state and processes accumulated interrupts. This dynamic adaptation resolves the contradiction by making interrupt handling flexible rather than static.

Inventive Principle:
Principle #15Dynamics

2Use of energy by moving object

If the CPU enters idle state for longer periods, then power consumption is reduced, but interrupt handling performance deteriorates

Engineering Contradiction:
Improvepower consumptionVSAvoidinterrupt handling performance
Core Design Contradiction:
Use of energy by moving objectVSProductivity

Solution Approach 1:

The interrupt handling system is segmented into two distinct pathways: maskable interrupts that can be delayed and accumulated, and non-maskable interrupts that must be handled immediately. This segmentation allows the CPU to extend idle states for maskable interrupts while ensuring non-maskable interrupts receive immediate attention, thus maintaining overall interrupt handling performance while reducing power consumption during idle periods.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system performs preliminary classification of interrupts into maskable and non-maskable categories before processing. By anticipating which interrupts can be delayed and which cannot, the system prepares in advance to extend idle states safely, reducing unnecessary transitions from idle to active states and thereby lowering power consumption while maintaining responsive performance for critical interrupts.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP3717987B1Dynamic interrupt rate control in computing systems
Publication Date: 2023.04.19 ADVANCED MICRO DEVICES INC
  • EP3717987B1 patent drawingFigure 1
  • EP3717987B1 patent drawingFigure 2
  • EP3717987B1 patent drawingFigure 3

AI summary

Systems, apparatuses, and methods for intentionally delaying servicing of interrupts in a computing system are disclosed. A computing system includes a processor that services interrupts generated by components of the computing system. An interrupt controller detects a received interrupt and intentionally delays servicing of the interrupt depending on various conditions. If the interrupt is a first type of interrupt and the processor is in a first power state, servicing of the interrupt is delayed by a first period of time. If the interrupt corresponds to the first type of interrupt and the processor is in a second power state, servicing of the interrupt is delayed for a period of time that is longer than the first period of time. If a non-maskable interrupt is received before expiration of either the first or second period of time, then servicing of any previously delayed interrupts is allowed to proceed.