Dynamic Input Verification for I/O Components

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Solution Overview

Problem

Traditional verification methods for input/output components fail to adequately test their operation under dynamic and varied conditions, as they rely on static input patterns and matched data rates, which do not reflect actual operating environments.

Innovation Solution

A system and method that utilize multiple queues and call backs to simulate dynamic input and output conditions, allowing for random data processing and prediction of output ordering, error handling, and data queuing, enabling verification of input/output devices across various host and bus types without static stimulus patterns.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional static input patterns are used for verification, then the verification process is simple and controlled, but the verification does not reflect actual operating environments and fails to adequately test the component

Engineering Contradiction:
Improveverification accuracyVSAvoidverification system complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The verification system transitions from static predetermined input patterns to dynamic input generation that adapts during verification. The system now generates input patterns dynamically based on component behavior and verification progress, allowing the verification environment to reflect actual operating conditions while maintaining controllability through algorithmic generation.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The verification system generates its own input patterns autonomously based on the component's operational characteristics and verification requirements. Rather than relying on externally predetermined static patterns, the system self-adapts by generating appropriate test inputs during the verification process itself, making the verification more representative of real operating environments.

Inventive Principle:
Principle #25Self-service

2Reliability

If data rates are matched between input and output sides of the component, then data loss is prevented during testing, but the testing environment becomes unrealistic as actual operating conditions rarely have matched data rates

Engineering Contradiction:
Improvedata integrity during testingVSAvoidtesting environment realism
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The verification system dynamically adjusts data rate parameters during testing to reflect realistic operating conditions. Instead of maintaining fixed matched data rates, the system varies input and output data rates independently to simulate actual operational scenarios, while still ensuring data integrity through proper buffering and synchronization mechanisms.

Inventive Principle:
Principle #35Parameter changes

3Ease of operation

If predetermined static input sets are used to test different functionality, then each test case is controlled and reproducible, but multiple separate static sets are required and the testing does not cover the full range of operational conditions

Engineering Contradiction:
Improvetest case controlVSAvoidfunctional coverage
Core Design Contradiction:
Ease of operationVSAdaptability or versatility

Solution Approach 1:

The verification system employs a universal dynamic input generation mechanism that can produce diverse test patterns for different functional areas without requiring separate static input sets. This single versatile system adapts its input generation based on which component functionality is being tested, providing both control and comprehensive coverage.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS8078928B2System and method for verifying the transmit path of an input/output component
Publication Date: 2011.12.13 ORACLE AMERICAN INC
  • US8078928B2 patent drawing
  • US8078928B2 patent drawing
  • US8078928B2 patent drawing

AI summary

A system and method for verifying the transmit path of an input/output device such as a network interface circuit. The device's operation with various different input sources (e.g., hosts, input buses) and output sources (e.g., output buses, networks) is modeled in a verification layer that employs multiple queues to simulate receipt of input data, submission to an output port and transmission from the device. Call backs are employed to signal completion of events related to receipt of data at the device and modeling of data processing within the verification layer. As call backs are resolved, corresponding tasks are executed to advance the processing of the data through the verification layer. A device-specific algorithm is executed in the verification layer to predict the ordering of output from the device, and that output is compared to the predicted output by a transmission checker.