Dynamic Latch Bootstrap Clocking for Leakage Control
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Solution Overview
Problem
The reduction in gate width and parasitic capacitor capacitance of dynamic latches leads to increased leakage current and reduced storage time, affecting the ability to meet minimum operating frequencies and store logic data reliably.
Innovation Solution
A latch calibration system and latch driving system are introduced, utilizing bootstrap circuits to generate enhanced clock control signals with adjusted voltage levels to tighten the channel conductance of transistors, preventing leakage current and ensuring accurate data storage and retrieval at minimum operating frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the gate width of dynamic latch components is reduced for power-saving design, then power consumption is reduced, but leakage current increases and storage time decreases
Solution Approach 1:
The calibration circuit performs preliminary adjustment of clock control signal voltage levels before the dynamic latch operates at minimum frequency. By pre-calibrating the voltage levels to compensate for expected leakage effects, the system maintains reliable data storage even with reduced gate width and lower power consumption.
Solution Approach 2:
The invention dynamically adjusts the voltage level parameter of clock control signals based on calibration results. The calibration circuit modifies the voltage levels of clock control signals to optimize the trade-off between power consumption and leakage current, allowing the system to operate reliably at reduced power levels.
2Use of energy by moving object
If the gate width of dynamic latch components is reduced for power-saving design, then power consumption is reduced, but storage time decreases
Solution Approach 1:
The calibration circuit performs preliminary adjustment of clock control signal voltage levels before the dynamic latch operates at minimum frequency. By pre-calibrating the voltage levels to compensate for expected leakage effects, the system maintains reliable data storage even with reduced gate width and lower power consumption.
Solution Approach 2:
The invention dynamically adjusts the voltage level parameter of clock control signals based on calibration results. The calibration circuit modifies the voltage levels of clock control signals to optimize the trade-off between power consumption and leakage current, allowing the system to operate reliably at reduced power levels.
3Use of energy by moving object
If the capacitance value of parasitic capacitor is reduced, then power consumption is reduced, but leakage current increases
Solution Approach 1:
The calibration circuit performs preliminary adjustment of clock control signal voltage levels before the dynamic latch operates at minimum frequency. By pre-calibrating the voltage levels to compensate for expected leakage effects, the system maintains reliable data storage even with reduced gate width and lower power consumption.
Solution Approach 2:
The invention dynamically adjusts the voltage level parameter of clock control signals based on calibration results. The calibration circuit modifies the voltage levels of clock control signals to optimize the trade-off between power consumption and leakage current, allowing the system to operate reliably at reduced power levels.
4Speed
If the minimum operating frequency is increased, then system performance is improved, but power consumption increases
Solution Approach 1:
The system dynamically adjusts the voltage levels of clock control signals based on calibration results to enable operation at minimum frequency. This dynamic adaptation allows the latch to maintain reliable performance at lower frequencies without requiring higher power consumption, optimizing the frequency-power trade-off.
Data Source
AI summary
A latch calibration system includes a latch, a clock circuit and a calibration circuit. Latch latches logic data from a data node in an internal node. Latch includes two transistors respectively coupled between data node and internal node. Clock circuit generates first and second clock control signals. Calibration circuit is coupled to clock circuit and latch, and includes two bootstrap circuits coupled to clock circuit respectively. First bootstrap circuit generates a third clock control signal according to first clock control signal, which is output to a gate of first transistor. a high level of third clock control signal is greater than that of first clock control signal. Second bootstrap circuit generates a fourth clock control signal according to the second clock control signal, which is output to a gate of second transistor. A low level of fourth clock control signal is less than that of second clock control signal.