Dynamic Latch Data Pipeline for Wide Clock Phase Tuning
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Solution Overview
Problem
Conventional data pipeline architectures face limitations in achieving high data throughput and decoupling pre- and post-register timing due to restricted clock phase relationships, particularly in noisy environments, which restricts the tuning range and increases propagation delay.
Innovation Solution
A data pipeline architecture utilizing a flip-flop and dynamic latch stages, where the dynamic latch is configured to be in transparent mode only for a short period, allowing a wide range of clock phase shifting and using cross-coupled inverters with feedback transfer elements to control state changes, along with delayed clock signals to manage data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the phase of the second clock CLK2 is shifted closer to the phase of the first clock CLK1 to speed up data transfer, then the data transfer rate is improved, but the propagation delay time of the first flip-flop FF1 and set-up time of the second flip-flop FF2 limit the tuning range to approximately four gate delays
Solution Approach 1:
The patent employs a dynamic latch instead of a static flip-flop for the second stage. The dynamic latch can be switched between transparent and non-transparent modes by controlling the second clock signal phase, enabling flexible adjustment of the timing relationship between stages. This dynamic behavior allows the system to adapt to different timing requirements while maintaining fast data transfer.
Solution Approach 2:
The invention changes the operational parameters of the latch by controlling its transparency window through the second clock phase. By adjusting the phase of CLK2 relative to CLK1 and controlling when the latch enters transparent mode, the system can optimize both data transfer speed and timing decoupling. The latch remains non-transparent during most of the clock period and only becomes transparent for a limited time window.
2Speed
If the latch is switched into transparent mode before data arrives at Q1 to achieve fastest data transfer rate, then the data transfer speed is improved, but the pre- and post-register timing cannot be decoupled
Solution Approach 1:
The patent uses the first clock signal CLK1 to pre-charge or prepare the dynamic latch before data arrives from the first flip-flop. This preliminary action ensures that when data is transferred, the latch is already in the correct state to capture it reliably, while still maintaining timing decoupling between the noisy input stage and the clean output stage.
Solution Approach 2:
The dynamic latch operates in periodic transparent and non-transparent modes synchronized with the clock signals. This periodic operation allows the latch to be transparent only during specific time windows when data transfer is intended, while remaining non-transparent during other periods to maintain timing decoupling and prevent noise propagation.
3Reliability
If the latch is switched into non-transparent mode before new data arrives at Q1 to decouple pre- and post-register timing, then timing decoupling is achieved, but the tuning range of the second clock phase is limited to less than 180 degrees
Solution Approach 1:
The dynamic latch provides dynamic control over its transparency state, allowing the system to achieve both timing decoupling and extended tuning range. By controlling when the latch transitions to and from transparent mode through the second clock signal, the system can maintain reliability while expanding the adjustable phase range beyond the limitations of static configurations.
Data Source
AI summary
The invention relates to a data pipeline comprising a first stage with a data input for receiving a digital data input signal, a clock input and a data output, and a first bi-stable element being adapted to be switched in response to an edge of a first clock signal, and a dynamic latch stage comprising an input transfer element, and a second bi-stable element coupled between the input transfer element and a dynamic latch data output, wherein the input transfer element is adapted to be switched by a second clock signal and a delayed second clock signal, which is delayed with respect to the second clock signal by a first period of time being shorter than half a period of the second clock signal, such that the input transfer element allows signal transfer only during the first period of time.