Dynamic Latch Layout to Eliminate CNOD Leakage Paths

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Solution Overview

Problem

The implementation of continuous oxide diffusion (CNOD) regions in semiconductor devices leads to leakage issues in dynamic latches, causing anomalies due to parasitic transistors.

Innovation Solution

A dynamic latch design with two transmission gates and an inverter, where the drain regions of the transmission gates are on opposite sides and the source regions are between them, eliminating parasitic transistor influence and reducing leakage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If continuous oxide diffusion (CNOD) regions are implemented in semiconductor devices, then manufacturing efficiency and integration are improved, but leakage issues occur in dynamic latches due to parasitic transistors

Engineering Contradiction:
Improvemanufacturing efficiencyVSAvoidleakage performance
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent divides the oxide diffusion region into separate, non-continuous segments for different functional units. Specifically, the first oxide diffusion region is isolated from the second oxide diffusion region, preventing the formation of parasitic transistors at the interface while maintaining the manufacturing efficiency of oxide diffusion technology.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies different oxide diffusion configurations to different regions of the semiconductor device. The first functional unit has its own isolated oxide diffusion region, while the second functional unit has a separate oxide diffusion region, allowing each region to be optimized locally without affecting other regions, thus eliminating parasitic transistor formation.

Inventive Principle:
Principle #3Local quality

2Adaptability or versatility

If oxide diffusion regions of respective functional units are continuous, then device integration is improved, but parasitic transistors form causing leakage in dynamic latches

Engineering Contradiction:
Improvedevice integrationVSAvoidparasitic transistors
Core Design Contradiction:
Adaptability or versatilityVSObject-generated harmful factors

Solution Approach 1:

The patent segments the oxide diffusion regions so that the first oxide diffusion region and the second oxide diffusion region are spatially separated and do not connect. This segmentation prevents the formation of parasitic transistors that would occur with continuous oxide diffusion, while still achieving high device integration through careful layout of the separated regions.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent extracts or removes the harmful continuous oxide diffusion path between functional units. By taking out the connecting oxide diffusion region that would create parasitic transistors, the design maintains functional unit independence and eliminates leakage while preserving integration benefits.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS12451887B2Dynamic latch, semiconductor chip, computing power board and computing device
Publication Date: 2025.10.21 BEIJING BITMAIN TECHNOLOGIES
  • US12451887B2 patent drawing
  • US12451887B2 patent drawing
  • US12451887B2 patent drawing

AI summary

Provided is a dynamic latch, including: a substrate; a data transmission unit, including a first transmission gate and a second transmission gate, in which an input end of the first transmission gate is connected to an input end of the second transmission gate, and an output end of the first transmission gate is connected to an output end of the second transmission gate; a data output unit, including a first inverter, in which an input end of the first inverter is connected to the output ends of the two transmission gates, a first region of the substrate is adjacent to a second region thereof and oxide diffusion regions in two regions are continuous, drain regions of the two transmission gates are respectively located on opposite sides in the first region, and source regions of the two transmission gates are located between the drain regions of the two transmission gates.