Dynamic Latch Leakage Compensation for Longer Data Retention
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Solution Overview
Problem
Dynamic latches face challenges in retaining data due to charge leakage, leading to the need for frequent refresh cycles, which increases power consumption and may not be suitable for all devices, especially those requiring high-speed operations and low power consumption.
Innovation Solution
A dynamic latch design with a minimal number of transistors that includes compensation circuits to extend data retention time, reducing the need for frequent refresh cycles and lowering power consumption by maintaining data validity for a longer interval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If dynamic latches are used to achieve high-speed operations and low power consumption, then operating speed and power efficiency are improved, but charge leakage occurs leading to short data retention time requiring frequent refresh cycles
Solution Approach 1:
The patent applies preliminary anti-action by introducing compensation transistors (first and second compensation transistors) that proactively counteract charge leakage effects before data becomes invalid. These transistors are configured to compensate for charge loss in the memory node, extending the retention time of stored data without requiring frequent refresh cycles, thus resolving the contradiction between high-speed operation and short data retention time
2Reliability
If refresh rate is increased to maintain data validity before leakage causes data to become invalid, then data retention reliability is improved, but power consumption increases
Solution Approach 1:
The patent implements self-service through compensation circuits that automatically detect and correct charge leakage in the memory node without external intervention. The compensation transistors are controlled by control signals that activate them based on the actual charge state, allowing the latch to self-correct and maintain data validity continuously, thereby reducing the need for frequent high-power refresh cycles while maintaining reliability
3Duration of action of stationary object
If static latches are used to avoid refresh cycles and extend data retention time, then data retention time is improved, but device size and power consumption increase
Solution Approach 1:
The patent merges the advantages of dynamic latches (small size, high speed, low power) with the advantage of static latches (long data retention) by combining dynamic latch structure with compensation circuits. The compensation transistors are integrated into the dynamic latch architecture, creating a hybrid structure that achieves extended retention time without the large size penalty of traditional static latches
Data Source
AI summary
Some embodiments include input stage of a latch to receive input data information and clock information; a memory node coupled to the input stage to store information based on the input data information; an output stage of the latch coupled to the memory node and including an output node to provide output data information based on the information stored at the memory node; a first circuit to provide a first circuit path between the memory node and a first node in the input stage; and a second circuit to provide a second circuit path between the memory node and a second node in the input stage.