Leakage-Compensated Dynamic Latch for Longer Data Retention
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Solution Overview
Problem
Dynamic latches face challenges in retaining data due to charge leakage, leading to increased refresh rates and power consumption, which is undesirable in devices where size, speed, and power efficiency are concerns.
Innovation Solution
A dynamic latch design with a minimal number of transistors and additional compensation circuits that extend data retention time, reducing the need for frequent refresh cycles and lowering power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If dynamic latch size is reduced to increase integration density, then device area is improved, but charge leakage increases causing data retention to deteriorate
Solution Approach 1:
The latch is divided into two functional parts: a retention circuit (first circuit) that maintains the stored charge on the memory node, and a read circuit (second circuit) that retrieves the data. This segmentation allows the retention circuit to be optimized for minimal leakage with fewer transistors, while the read circuit handles the data output function.
Solution Approach 2:
The first node serves multiple functions: it stores the complement data during the write phase and continues to hold this charge during the retention phase to compensate for leakage. This multi-functional use of the first node and its associated transistor reduces the need for additional dedicated retention transistors.
2Reliability
If refresh rate is increased to compensate for charge leakage, then data retention is improved, but power consumption increases
Solution Approach 1:
The retention circuit proactively compensates for charge leakage by maintaining a compensating charge on the memory node through the first transistor connected to the first node. This preliminary action prevents charge loss before it occurs, eliminating the need for frequent reactive refresh operations.
Solution Approach 2:
The latch circuit uses its own internal nodes and transistors to compensate for charge leakage. The first transistor and first node work together with the memory node to automatically maintain the stored charge, making the circuit self-sustaining without requiring external refresh control logic.
3Reliability
If static latch is used to avoid refresh cycles, then data retention is improved, but device area and power consumption increase
Solution Approach 1:
The invention extracts the retention function from the traditional dynamic latch structure and implements it separately using the first transistor and first node. This allows the main latch structure to remain compact while adding minimal components for retention, achieving static-like data retention with dynamic latch area efficiency.
Data Source
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AI summary
Some embodiments include input stage of a latch to receive input data information and clock information; a memory node coupled to the input stage to store information based on the input data information; an output stage of the latch coupled to the memory node and including an output node to provide output data information based on the information stored at the memory node; a first circuit to provide a first circuit path between the memory node and a first node in the input stage; and a second circuit to provide a second circuit path between the memory node and a second node in the input stage.