Dynamic Latch Circuit for Low-Power High-Speed Operation
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Solution Overview
Problem
Current-mode logic (CML) latch circuits consume higher power due to direct current (DC) power paths, outpacing complementary metal oxide semiconductor (CMOS) counterparts in power consumption, while maintaining operational speed in high-data-rate applications.
Innovation Solution
Incorporating a switching device between the non-inverting and inverting output nodes of the latch circuit, which is turned on during a pre-evaluate phase to reduce voltage difference and turned off during a regenerate phase, achieving power consumption comparable to CMOS while maintaining operational speed comparable to CML.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If current-mode logic (CML) latch circuits are used to maintain operational speed in high-data-rate applications, then operational speed is improved, but power consumption increases due to direct current (DC) power paths
Solution Approach 1:
The patent applies dynamics by transitioning the latch circuit from a static DC power path architecture to a dynamic time-multiplexed architecture. The circuit alternates between a first DC power path during a first time period and a second DC power path during a second time period, allowing the power consumption to be dynamically controlled while maintaining high operational speed. This time-division multiplexing of power paths eliminates the continuous DC power consumption of traditional CML circuits while preserving their high-speed performance.
2Use of energy by moving object
If CMOS latch circuits are used to reduce power consumption, then power consumption is improved, but operational speed deteriorates compared to CML counterparts
Solution Approach 1:
The patent overcomes the speed limitation of CMOS circuits by implementing a dynamic time-multiplexed architecture that alternates between two DC power paths. During each time period, one power path is active while the other is inactive, enabling the circuit to achieve both low power consumption (comparable to CMOS) and high operational speed (comparable to CML). The rapid switching between power paths maintains signal integrity and timing requirements.
3Use of energy by moving object
If a switching device is added between output nodes to enable time-multiplexed power paths, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The switching devices in the patent serve multiple functions simultaneously: they act as power path selectors to enable time-multiplexed DC power paths, function as signal routing elements, and provide isolation between the two power paths. This multi-functionality reduces the need for additional dedicated components, thereby limiting the increase in circuit complexity while achieving significant power consumption reduction.
Data Source
AI summary
A latch circuit includes first and second supply nodes having a first voltage value and a second voltage below the first voltage value, first and second input nodes, first and second output nodes, a first switch coupled between the first and second output nodes and turned on and off responsive to first and second clock signal states, first and second transistors coupled between the respective second and first output nodes and the second supply node. A second switch is coupled between a first transistor gate and the first input node, a third switch is coupled between a second transistor gate and the second input node, and each is turned on and off responsive to the first and second states. During the first state, one of the first or second transistors is part of a low resistance path from the first power supply node to the second power supply node.