Dynamic Latch Page Buffer for Memory Area Reduction
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Solution Overview
Problem
The increasing integration density of memory devices has led to a demand for reducing the area occupied by the page buffer in peripheral circuits, necessitating a reduction in the number of elements constituting the page buffer.
Innovation Solution
A page buffer design that includes a first latch for storing program verification information, a second latch for storing first bit line forced information, and a dynamic latch for storing second bit line forced information, with the dynamic latch utilizing a control switch and a capacitor to store information, allowing for efficient bit line forcing operations without additional latch structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If traditional latch structures are used for storing bit line forced information, then reliable data storage is achieved, but the area occupied by the page buffer increases
Solution Approach 1:
The patent applies the dynamics principle by using a dynamic latch structure that utilizes a capacitor to store bit line forced information dynamically during the programming operation. This capacitor-based storage is temporary and operation-specific, allowing the page buffer to reduce its component count and area occupation while maintaining the necessary functionality for bit line forcing operations during the programming sequence.
2Area of stationary object
If the number of latch structures is reduced to decrease area, then area occupation is reduced, but the complexity of managing multiple bit line forced information states increases
Solution Approach 1:
The patent merges the storage function for first and second bit line forced information into a single dynamic latch structure using one capacitor. By combining multiple information storage requirements into a unified dynamic storage mechanism, the page buffer reduces the total number of components while managing the complexity through integrated control logic that coordinates the single capacitor's state with the programming operation phases.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed page buffer design effectively reduces the number of components while maintaining efficient bit line forcing operations, thereby optimizing the area usage in memory device peripheral circuits.
Implementation Method 1
the dynamic latch is configured to store information through a capacitor to which the control switch is coupled
Data Source
AI summary
In one aspect, a page buffer includes a first latch configured to store program verification information; a second latch configured to store first bit line forced information; and a dynamic latch configured to store second bit line forced information. The first bit line forced information is different from the second bit line forced information. The dynamic latch includes a control switch coupled to the second latch. And the dynamic latch is configured to store information through a capacitor to which the control switch is coupled.