Dynamic Latch Retention Circuit for High-Frequency Data Integrity

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Solution Overview

Problem

Existing dynamic latches and flip-flops suffer from insufficient data retention time due to dynamic leakage current, leading to data loss and reduced operational accuracy as the operation frequency increases.

Innovation Solution

A dynamic latch and D flip-flop design that incorporates a data retention unit connected to a node between the data transmission and output units, utilizing PMOS and NMOS transistors to extend data retention time and improve data security and accuracy.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the operation frequency is increased to improve processing speed, then productivity is improved, but data retention time decreases due to dynamic leakage current

Engineering Contradiction:
Improveoperation frequencyVSAvoiddata retention time
Core Design Contradiction:
ProductivityVSDuration of action of moving object

Solution Approach 1:

The latch circuit is divided into two separate latches (first latch and second latch) that operate in a pipeline manner. Each latch has dedicated retention units (first retention unit and second retention unit) that independently maintain data for their respective stages, allowing the overall system to operate at higher frequencies without compromising individual data retention requirements.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Retention units are introduced as intermediary components between the transmission and output stages of each latch. These retention units act as buffer elements that temporarily hold data during the critical period when high-frequency operation would otherwise cause data loss due to leakage current.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If dynamic leakage current is reduced to improve data retention, then data security is improved, but operation frequency must be reduced

Engineering Contradiction:
Improvedata securityVSAvoidoperation frequency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

By segmenting the single latch into two latches with separate retention units, each retention unit can be optimized for data security independently. The first retention unit secures data in the first latch while the second retention unit secures data in the second latch, allowing both to maintain high reliability even at elevated operating frequencies.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The retention units perform preliminary data preservation actions before the data would be lost to leakage current. By proactively maintaining data in the retention units during the latch operation cycle, the system prevents data loss before it occurs, enabling higher frequencies without sacrificing security.

Inventive Principle:
Principle #10Preliminary action

3Duration of action of moving object

If a data retention unit is added to extend data retention time, then data retention time is improved, but device complexity increases

Engineering Contradiction:
Improvedata retention timeVSAvoidcircuit complexity
Core Design Contradiction:
Duration of action of moving objectVSDevice complexity

Solution Approach 1:

The retention units are merged with the latch structures in an integrated manner. The first retention unit is combined with the first latch, and the second retention unit is combined with the second latch, forming unified pipeline stages. This merging approach extends data retention functionality without requiring completely separate, additional circuit blocks.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The retention units serve multiple functions: they extend data retention time, enable higher operating frequencies, and maintain data security simultaneously. By designing these units to perform multiple critical functions, the added complexity is justified by the multiple benefits achieved, and the same structural pattern can be replicated in the pipeline.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20250150068A1Dynamic latch, dynamic d flip-flop, data operation unit, chip, hash board, and computing device
Publication Date: 2025.05.08 CANAAN CREATIVE (SH) CO LTD
  • US20250150068A1 patent drawing
  • US20250150068A1 patent drawing
  • US20250150068A1 patent drawing

AI summary

The invention provides a dynamic latch, comprising an input terminal for inputting a first data; an output terminal for outputting a second data; a clock signal terminal for supplying a clock signal; a data transmission unit for transmitting the first data under control of the clock signal; and a data output unit for converting the first data into the second data. The data transmission unit and the data output unit are sequentially connected in series between the input terminal and the output terminal, and a node is provided between the data transmission unit and the data output unit. The dynamic latch further comprises a data retention unit electrically connected to the node. The retention time of data can be effectively extended, thereby improving data security and accuracy.